Results 21 to 30 of about 303,516 (284)
A RRAM Integrated 4T SRAM with Self-Inhibit Resistive Switching Load by Pure CMOS Logic Process
Nanoscale Research Letters, 2017 This paper reports a novel full logic compatible 4T2R non-volatile static random access memory (nv-SRAM) featuring its self-inhibit data storing mechanism for in low-power/high-speed SRAM application.
Meng-Yin Hsu +4 more
doaj +1 more source
Active and Passive Electronic Components, 2023 Combining with a static random-access memory (SRAM) and resistive memory (RRAM), an improved 8T2R nonvolatile SRAM (nvSRAM) memory cell is proposed in this study. With differential mode, a pair of 1T1R RRAM is added to 6T SRAM storage node. By optimizing
Jiayu Yin, Wenli Liao, Chengying Chen
doaj +1 more source
March AB, a State-of-the-Art March Test for Realistic Static Linked Faults and Dynamic Faults in SRAMs [PDF]
, 2007 Memory testing commonly faces two issues: the characterisation of detailed and realistic fault models, and the definition of time-efficient test algorithms able to detect them.
Bosio, Alberto +3 more
core +1 more source
Sensors, 2023 This paper introduces an n-type pseudo-static gain cell (PS-nGC) embedded within dynamic random-access memory (eDRAM) for high-speed processing-in-memory (PIM) applications.
Subin Kim, Ingu Jeong, Jun-Eun Park
doaj +1 more source
Influence of parasitic capacitance variations on 65 nm and 32 nm predictive technology model SRAM core-cells [PDF]
, 2008 The continuous improving of CMOS technology allows the realization of digital circuits and in particular static random access memories that, compared with previous technologies, contain an impressive number of transistors.
Di Carlo, Stefano +3 more
core +1 more source
Technology and layout-related testing of static random-access memories [PDF]
Journal of Electronic Testing, 1994 Static random-access memories (SRAMs) exhibit faults that are electrical in nature. Functional and electrical testing are performed to diagnose faulty operation. These tests are usually designed from simple fault models that describe the chip interface behavior without a thorough analysis of the chip layout and technology.
Chakraborty, Kanad, Mazumder, Pinaki
openaire +2 more sources
A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs [PDF]
, 2006 Among the different types of algorithms proposed to test static random access memories (SRAMs), march tests have proven to be faster, simpler and regularly structured.
Benso, Alfredo +4 more
core +1 more source
March Test Generation Revealed [PDF]
, 2008 Memory testing commonly faces two issues: the characterization of detailed and realistic fault models and the definition of time-efficient test algorithms.
Benso, Alfredo +4 more
core +2 more sources
Effects of total ionizing dose on transient ionizing radiation upset sensitivity of 40–180 nm SRAMs
AIP Advances, 2022 Effects of total ionizing dose (TID) on the transient radiation upset sensitivity of commercial static random access memories (SRAMs) were investigated.
Junlin Li +8 more
doaj +1 more source
Efficient Gauss Elimination for Near-Quadratic Matrices with One Short Random Block per Row, with Applications [PDF]
, 2019 In this paper we identify a new class of sparse near-quadratic random Boolean matrices that have full row rank over F_2 = {0,1} with high probability and can be transformed into echelon form in almost linear time by a simple version of Gauss elimination.
Dietzfelbinger, Martin, Walzer, Stefan
core +3 more sources