Results 121 to 130 of about 1,678 (162)

Forest-EMCBE: an evolutionary ensemble learning algorithm for multiclass diagnosis of bacterial pneumonia using the CBC dataset. [PDF]

Front Bioinform
Shen Y, Xu X, Hao X, Sun C, Lan W.
europepmc   +1 more source

A Pipeline for Automating Emergency Medicine Documentation Using LLMs with Retrieval-Augmented Text Generation. [PDF]

Appl Artif Intell
Moser D, Bender M, Sariyar M.
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Magnetization dynamics: From the Landau-Lifschitz equation to spintronics. [PDF]

Struct Dyn
Acremann Y.
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Exploring Applications of STT-RAM in GPU Architectures

IEEE Transactions on Circuits and Systems I: Regular Papers, 2021
Use of modern GPUs has been extended from traditional 3D graphic processing to computing acceleration of many scientific, engineering, and enterprise applications. In modern GPUs, on-chip memory capacity keeps increasing to support thousands of chip-resident threads.
Xiaoxiao Liu, Mengjie Mao, Xiuyuan Bi, Hai Li, Yiran Chen   +4 more
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Multi-level cell STT-RAM

Proceedings of the International Conference on Computer-Aided Design, 2012
Spin-transfer torque random access memory (STT-RAM) is a promising nonvolatile memory technology aiming on-chip or embedded applications. In recent years, many researches have been conducted to improve the storage density and enhance the scalability of STT-RAM, such as reducing the write current and switching time of magnetic tunneling junction (MTJ ...
Yaojun Zhang, Lu Zhang, Wujie Wen, Guangyu Sun, Yiran Chen   +4 more
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Compiler-Assisted Refresh Minimization for Volatile STT-RAM Cache

IEEE Transactions on Computers, 2013
Spin-Transfer Torque RAM (STT-RAM) has been proposed to build on-chip caches because of its attractive features: high storage density and negligible leakage power. Recently, researchers propose to improve the write performance of STT-RAM by relaxing its non-volatility property. To avoid data loss resulting from volatility, refresh schemes are proposed.
null Qingan Li, null Jianhua Li, null Liang Shi, C. J. Xue, null Yiran Chen, null Yanxiang He   +5 more
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Self-Terminated Write-Assist Technique for STT-RAM

IEEE Transactions on Magnetics, 2016
The main challenge in the programming of spin transfer torque (STT)-RAM is to reduce the associated power consumption without the increase in area. This paper proposes a novel self-terminated write-assist technique to cutoff the unnecessary writing power consumption and then compares its delay and writing power consumption with the previously reported ...
Mohit Kumar Gupta, Mohd. Hasan
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Endurance enhancement of write-optimized STT-RAM caches

Proceedings of the International Symposium on Memory Systems, 2019
Low density and high leakage power of SRAM are the major setbacks for its scalability. Non-volatile memory (NVM) like spin-transfer torque random access memory (STT-RAM) is a suitable replacement for SRAM at the last level cache (LLC). NVM offers high density, and near zero leakage, which are highly desired for on-chip caches.
Puneet Saraf, Madhu Mutyam
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Ternary cache: Three-valued MLC STT-RAM caches

2014 IEEE 32nd International Conference on Computer Design (ICCD), 2014
Spin-transfer torque random access memory (STT-RAM) has become a promising non-volatile memory technology for cache memories. Recently, 2-bit multi-level cell (MLC) STT-RAM has been proposed to enhance data density, but it suffers from low reliability of its read and write operations. In this paper, we propose a novel cache design called Ternary cache.
Seokin Hong, Jongmin Lee, Soontae Kim
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An efficient STT-RAM last level cache architecture for GPUs

2014 51st ACM/EDAC/IEEE Design Automation Conference (DAC), 2014
In this paper, having investigated the behavior of GPGPU applications, we present an efficient L2 cache architecture for GPUs based on STT-RAM technology. With the increase of processing cores count, larger on-chip memories are required. Due to its high density and low power characteristics, STT-RAM technology can be utilized in GPUs where numerous ...
Mohammad Hossein Samavatian, Hamed Abbasitabar, Mohammad Arjomand, Hamid Sarbazi-Azad   +3 more
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