Results 11 to 20 of about 141,240 (252)

Subthreshold Swing in Silicon Gate-All-Around Nanowire and Fully Depleted SOI MOSFETs at Cryogenic Temperature

open access: yesIEEE Journal of the Electron Devices Society, 2021
Subthreshold swing (SS) in a silicon gate-all-around (GAA) nanowire MOSFET with zero body factor is examined from room temperature (RT) down to 4 K. A fully depleted (FD) SOI MOSFET is also evaluated.
Shohei Sekiguchi   +5 more
doaj   +2 more sources

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects. [PDF]

open access: yesNano Lett, 2020
Nanowire tunnel field-effect transistors (TFETs) have been proposed as the most advanced one-dimensional (1D) devices that break the thermionic 60 mV/decade of the subthreshold swing (SS) of metal oxide semiconductor field-effect transistors (MOSFETs) by
Saeidi A   +6 more
europepmc   +2 more sources

Effects of Charge Trapping at the MoS2-SiO2 Interface on the Stability of Subthreshold Swing of MoS2 Field Effect Transistors. [PDF]

open access: yesMaterials (Basel), 2020
The stability of the subthreshold swing (SS) is quite important for switch and memory applications in logic circuits. The SS in our MoS2 field effect transistor (FET) is enlarged when the gate voltage sweep range expands towards the negative direction ...
Huang X   +5 more
europepmc   +2 more sources

Physics-Based and Closed-Form Model for Cryo-CMOS Subthreshold Swing [PDF]

open access: yesIEEE transactions on nanotechnology, 2022
Cryogenic semiconductor device models are essential in designing control systems for quantum devices and in benchmarking the benefits of cryogenic cooling for high-performance computing.
A. Beckers   +9 more
semanticscholar   +1 more source

Subthreshold Swing of 59 mV decade−1 in Nanoscale Flexible Ultralow‐Voltage Organic Transistors

open access: yesAdvanced Electronic Materials, 2022
Organic thin‐film transistors (TFTs) that provide subthreshold swings near the theoretical limit together with large on/off current ratios at very low operating voltages require high‐capacitance gate dielectrics with a vanishingly small defect density. A
Michael Geiger   +9 more
semanticscholar   +1 more source

Enhancement-Mode Gate-Recess-Free GaN-Based p-Channel Heterojunction Field-Effect Transistor With Ultra-Low Subthreshold Swing

open access: yesIEEE Electron Device Letters, 2021
We report enhancement-mode ${p}$ -channel heterojunction field-effect transistors (HFETs) without gate recess on a standard ${p}$ -GaN/AlGaN/GaN high electron mobility transistor (HEMT) platform.
Chen Yang   +8 more
semanticscholar   +1 more source

Simulation of a Steep-Slope p- and n-Type HfS2/MoTe2 Field-Effect Transistor with the Hybrid Transport Mechanism

open access: yesNanomaterials, 2023
The use of a two-dimensional (2D) van der Waals (vdW) metal-semiconductor (MS) heterojunction as an efficient cold source (CS) has recently been proposed as a promising approach in the development of steep-slope field-effect transistors (FETs).
Juan Lyu, Jian Gong
doaj   +1 more source

Unified Analytic Framework for Thickness‐Dependent Transport and Trap‐State Modulation in Ultrathin W:In2O3 Field‐Effect Transistors

open access: yesSmall Structures
3D integration demands ultrathin oxide transistors that combine strong gate control, high mobility, steep subthreshold swing, and normally off operation within back‐end‐of‐line (BEOL) thermal budgets below 400°C.
Mochamad Januar   +3 more
doaj   +2 more sources

Theoretical Limit of Low Temperature Subthreshold Swing in Field-Effect Transistors

open access: yesIEEE Electron Device Letters, 2020
This letter reports a temperature-dependent limit for the subthreshold swing in MOSFETs that deviates from the Boltzmann limit at deep-cryogenic temperatures.
A. Beckers, F. Jazaeri, C. Enz
semanticscholar   +1 more source

Inductive line tunneling FET using epitaxial tunnel layer with Ge-source and charge enhancement insulation

open access: yesDiscover Nano, 2023
In this paper, we propose an inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET).
Jyi-Tsong Lin, Yen-Chen Chang
doaj   +1 more source

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