Results 31 to 40 of about 2,685 (210)

Investigation on Tunneling-based Ternary CMOS with Ferroelectric-Gate Field Effect Transistor Using TCAD Simulation

Applied Sciences, 2020
Ternary complementary metal-oxide-semiconductor technology has been spotlighted as a promising system to replace conventional binary complementary metal-oxide-semiconductor (CMOS) with supply voltage (VDD) and power scaling limitations.
Kitae Lee, Sihyun Kim, Daewoong Kwon, Byung-Gook Park   +3 more
doaj   +1 more source

Solution‐Processed Two‐Dimensional Indium Oxide on Sodium‐Embedded Alumina for Reconfigurable Optoelectronic Synaptic Transistors

Advanced Functional Materials, EarlyView.
Wafer‐scale two‐dimensioanl In2Se3 oxidized into InOx on sodium‐embedded beta‐alumina enables multifunctional reconfigurable electronics. Sodium ions accumulate within distinct spatial distribution under drain‐controlle and gate‐controlled operation. Drain‐control operation gives controllability of ultraviolet‐driven optoelectronic synaptic conductance
Jinhong Min, Yonghyun Albert Kwon, Hyunbin Kim, Jihyun Kim, Myeongjin Jung, Jaewon Heo, Gwang Ya Kim, Vlastimil Mazanek, Zdeněk Sofer, In Soo Kim, Jeong Ho Cho, Hyesung Park, Sang Min Won, Joohoon Kang   +13 more
wiley   +1 more source

Direct Channel Implantation of B and BF2 Ions for Functional Control of Oxygen Vacancies in Oxide Semiconductor Thin Film Transistors

Advanced Functional Materials, EarlyView.
Direct channel implantation of B and BF2 ions was employed to fabricate amorphous IGZO TFTs with improved electrical and stability properties. B and BF2 implantation modulate oxygen vacancies within the IGZO channel. The field‐effect mobility of ion‐implanted IGZO TFTs was enhanced as compared to pristine IGZO TFTs.
Beom Soo Kim, Jong Bin An, Seok Gyu Hong, Moon Ho Lee, Ju Hyun Lee, Ji Yeong Park, Hwa Seon Kim, I. Sak Lee, Kyungmoon Kwak, Hyun Jae Kim   +9 more
wiley   +1 more source

First Demonstration of Ultra-Thin SiGe-Channel Junctionless Accumulation-Mode (JAM) Bulk FinFETs on Si Substrate with PN Junction-Isolation Scheme

IEEE Journal of the Electron Devices Society, 2014
A SiGe-channel junctionless-accumulation-mode (JAM) PMOS bulk FinFETs were successfully demonstrated on Si substrate with PN junction-isolation scheme for the first time.
Dong-Hyun Kim, Tae Kyun Kim, Young Gwang Yoon, Byeong-Woon Hwang, Yang-Kyu Choi, Byung Jin Cho, Seok-Hee Lee   +6 more
doaj   +1 more source

Simultaneous Enhancement of Performance and Stability in Dual‐Gate a‐IGZO Thin‐Film Transistors via Single‐Step Laser Annealing for Capacitor‐Less DRAM

Advanced Functional Materials, EarlyView.
A single‐step laser annealing strategy is presented for dual‐gate a‐IGZO TFTs. The steep thermal gradient induces graded oxygen doping in the channel and simultaneous WOx removal at the contacts, enabling concurrent interface and contact engineering.
Sihyeon Kwon, Junil Kim, Geuntae Park, Minseok Kim, Woohyun Hwang, Wanki Kim, Daewon Ha, Byeongmoon Lee, Jae Eun Jang, Hyuk‐Jun Kwon   +9 more
wiley   +1 more source

Nonvolatile ferroelectric field-effect transistors

Nature Communications, 2020
There is growing interest in non-traditional materials for logic applications. Here, the authors demonstrate a domain device architecture based on ferroelectric LiNbO3 crystals with gate voltage controlled transistor without subthreshold swing and source
Xiaojie Chai, Jun Jiang, Qinghua Zhang, Xu Hou, Fanqi Meng, Jie Wang, Lin Gu, David Wei Zhang, An Quan Jiang   +8 more
doaj   +1 more source

Tunable Complementary Doping Strategy Enables High‐Performance Homo‐Channel CMOS in Monolayer WSe2

Advanced Functional Materials, EarlyView.
Polarity‐selective modulation enables a homo‐channel WSe2 CMOS platform from a single 2D semiconductor. MoOx and AlN tune WSe2 toward p‐ and n‐type operation, respectively, yielding complementary FETs and inverters with balanced switching, high voltage gain, low static power, and promising scalability for 2D logic integration.
Kuan‐Hsiang Chiu, Wen‐Chia Wu, His‐Yu Chen, Chien‐Chih Liu, Ze‐Rui Lin, Chiung‐Yuan Lin, Chenming Hu, Chao‐Hsin Chien   +7 more
wiley   +1 more source

The Influence of Gate Scaling to Electrical Characteristics on n-MOS FinFET

MATEC Web of Conferences, 2017
This paper investigates effects from gate scaling in Tri-gate FinFET structure by simulation method, to avoid problems and improve a structure to be good prototype. The experiments used GTS framework for simulation.
Patchrasardtra Nuttapong, Pengchan Weera
doaj   +1 more source

Ferroelectric Quantum Dots for Retinomorphic In‐Sensor Computing

Advanced Materials, EarlyView.
This work has provided a protocol for fabricating retinomorphic phototransistors by integrating ferroelectric ligands with quantum dots. The resulting device combines ferroelectricity, optical responsiveness, and low‐power operation to enable adaptive signal amplification and high recognition accuracy under low‐light conditions, while supporting ...
Tingyu Long, Huanyu Zhou, Jaewan Ko, Hongwei Tan, Jaemin Lim, Yanfei Zhao, Daehan Kang, Eojin Yoon, Gyeong‐Tak Go, Somin Kim, Seung‐Woo Lee, Chan‐Yul Park, Hyojun Choi, Hyeran Kim, Hyung Joong Yun, Sung Hyuk Park, Kwan Sik Park, Jeong Woo Park, Mungeun Kim, Yong Soo Cho, Ho Won Jang, Wenqiang Yang, Min Hyuk Park, Wan Ki Bae, Sebastiaan van Dijken, Joona Bang, Tae‐Woo Lee   +26 more
wiley   +1 more source

DC ANALYSIS OF p-n-p-n TUNNELING FIELD-EFFECT TRANSISTOR BASED ON In0.35Ga0.65As

Holos, 2018
Using calibrated simulations, we report the In0.35Ga0.65As based tunnel field-effect transistor (TFET) with thin δ-doped n+ pocket at the source-channel interface to improve the parameters such as  on current (Ion), off-current (Ioff) and subthreshold ...
Behnam Dorostkar, Saeid Marjani
doaj   +1 more source