Results 11 to 20 of about 2,685 (210)

Effect of Drain Induced Barrier Enhancement on Subthreshold Swing and OFF-State Current of Short Channel MOSFETs: A TCAD Study

open access: yesIEEE Access, 2021
In this paper, with the help of calibrated 2-D simulations, we report a detailed study on the effect of drain induced barrier enhancement on the subthreshold swing and OFF-state current of a short channel MOSFET.
Mamidala Karthik Ram   +3 more
doaj   +1 more source

Simulation of a Steep-Slope p- and n-Type HfS2/MoTe2 Field-Effect Transistor with the Hybrid Transport Mechanism

open access: yesNanomaterials, 2023
The use of a two-dimensional (2D) van der Waals (vdW) metal-semiconductor (MS) heterojunction as an efficient cold source (CS) has recently been proposed as a promising approach in the development of steep-slope field-effect transistors (FETs).
Juan Lyu, Jian Gong
doaj   +1 more source

Subthreshold Swing in Silicon Gate-All-Around Nanowire and Fully Depleted SOI MOSFETs at Cryogenic Temperature

open access: yesIEEE Journal of the Electron Devices Society, 2021
Subthreshold swing (SS) in a silicon gate-all-around (GAA) nanowire MOSFET with zero body factor is examined from room temperature (RT) down to 4 K. A fully depleted (FD) SOI MOSFET is also evaluated.
Shohei Sekiguchi   +5 more
doaj   +1 more source

Inductive line tunneling FET using epitaxial tunnel layer with Ge-source and charge enhancement insulation

open access: yesDiscover Nano, 2023
In this paper, we propose an inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET).
Jyi-Tsong Lin, Yen-Chen Chang
doaj   +1 more source

In-Line Tunnel Field Effect Transistor: Drive Current Improvement

open access: yesIEEE Journal of the Electron Devices Society, 2018
A new architecture of tunnel field effect transistor (TFET) with in-line (vertical) tunneling area is introduced. By adding the vertical tunneling area, the in-line TFET architecture outperformed the normal TFET in terms of the drive current, the ...
Woojin Park   +3 more
doaj   +1 more source

EFFECT OF FERRO ELECTRIC THICKNESS ON NEGATIVE CAPACITANCE FET (NCFET)

open access: yesInternational Islamic University Malaysia Engineering Journal, 2020
Conventional Field Effect Transistor (FET) are well known to require at least 60mV/decade at 300K change in the channel potential to change the current by a factor of 10. Due to this, 60mV/decade becomes the bottleneck of this day transistor.
Muhaimin Bin Mohd Hashim   +2 more
doaj   +1 more source

Improvement of Tunnel Field Effect Transistor Performance Using Auxiliary Gate and Retrograde Doping in the Channel [PDF]

open access: yesJournal of Electrical and Computer Engineering Innovations, 2018
Background and Objectives: In this work, a dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor (DWG SP RD-TFET) is proposed and investigated.Methods: The dual workfunction gate-source pocket-retrograde doping-tunnel ...
M. Karbalaei, D. Dideban, N. Moezi
doaj   +1 more source

Sensitivity Analysis of Biosensors Based on a Dielectric-Modulated L-Shaped Gate Field-Effect Transistor

open access: yesMicromachines, 2020
Label-free biomolecular sensors have been widely studied due to their simple operation. L-shaped tunneling field-effect transistors (LTFETs) are used in biosensors due to their low subthreshold swing, off-state current, and power consumption.
Chen Chong   +4 more
doaj   +1 more source

Structure-Dependent Subthreshold Swings for Double-gate MOSFETs

open access: yesJournal of information and communication convergence engineering, 2011
In this paper, subthreshold swing characteristics have been presented for double-gate MOSFETs, using the analytical model based on series form of potential distribution. Subthreshold swing is very important factor for digital devices because of determination of ON and OFF. In general, subthreshold swings have to be under 100mV/dec. The channel length L
Ji-Hyeong Han   +2 more
openaire   +2 more sources

Characterization and Modeling of 28-nm Bulk CMOS Technology Down to 4.2 K

open access: yesIEEE Journal of the Electron Devices Society, 2018
This paper presents an experimental investigation, compact modeling, and low-temperature physics-based modeling of a commercial 28-nm bulk CMOS technology operating at cryogenic temperatures. The physical and technological parameters are extracted at 300,
Arnout Beckers   +2 more
doaj   +1 more source

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