Results 21 to 30 of about 141,240 (252)

Chip-Scale Graphene/IGZO Cold Source FET Array Enabling Sub-60 mV dec^-1 Super-Steep Subthreshold Swing. [PDF]

Adv Mater
Super‐steep subthreshold swing (SS) below 60 mV dec−1 is demonstrated in graphene/IGZO cold source transistor arrays. Linear density of states with Dirac cone in graphene suppressed the Boltzmann thermal tail, while high‐k HfO2 dielectric having small body factor enhanced gating efficiency, hereby further reducing SS. An average SS of ≈46.4 mV dec−1 is
Oh S, Kwon O, Yoon J, Cho E, Kim MJ, Seo W, Kim M, Kim S, Kwon Y, Jung YJ, Kang K, Park W, Kim Y, Cho B.   +13 more
europepmc   +2 more sources

Cryogenic Subthreshold Swing Saturation in FD-SOI MOSFETs Described With Band Broadening [PDF]

IEEE Electron Device Letters, 2019
In the standard MOSFET description of the drain current $ {I}_{{D}}$ as a function of applied gate voltage $ {V}_{{ {GS}}}$ , the subthreshold swing ${{SS(T)}}\equiv {{dV}}_{{{GS}}}/ {d}\log {I}_{ {D}}$ has a fundamental lower limit as a function of
H. Bohuslavskyi, A. Jansen, S. Barraud, V. Barral, M. Cassé, L. Guevel, X. Jehl, L. Hutin, B. Bertrand, G. Billiot, G. Pillonnet, F. Arnaud, P. Galy, S. D. Franceschi, M. Vinet, M. Sanquer   +15 more
semanticscholar   +1 more source

Charge trapping mechanism leading to sub-60-mV/decade-Swing FETs [PDF]

, 2017
In this work, we present a novel method to reduce the subthreshold swing of field-effect transistors below 60 mV/dec. Through modeling, we directly relate trap charge movement between the gate electrode and the gate dielectric to subthreshold swing ...
Cantarella, Giuseppe, Daus, Alwin, Knobelspies, Stefan, Luisier, Mathieu, Munzenrieder, Niko, Petti, Luisa, Salvatore, Giovanni A, Troster, Gerhard, Vogt, Christian   +8 more
core   +1 more source

In-Line Tunnel Field Effect Transistor: Drive Current Improvement

IEEE Journal of the Electron Devices Society, 2018
A new architecture of tunnel field effect transistor (TFET) with in-line (vertical) tunneling area is introduced. By adding the vertical tunneling area, the in-line TFET architecture outperformed the normal TFET in terms of the drive current, the ...
Woojin Park, Amir N. Hanna, Arwa T. Kutbee, Muhammad Mustafa Hussain   +3 more
doaj   +1 more source

EFFECT OF FERRO ELECTRIC THICKNESS ON NEGATIVE CAPACITANCE FET (NCFET)

International Islamic University Malaysia Engineering Journal, 2020
Conventional Field Effect Transistor (FET) are well known to require at least 60mV/decade at 300K change in the channel potential to change the current by a factor of 10. Due to this, 60mV/decade becomes the bottleneck of this day transistor.
Muhaimin Bin Mohd Hashim, AHM Zahirul Alam, Naimah Binti Darmis   +2 more
doaj   +1 more source

Sensitivity Analysis of Biosensors Based on a Dielectric-Modulated L-Shaped Gate Field-Effect Transistor

Micromachines, 2020
Label-free biomolecular sensors have been widely studied due to their simple operation. L-shaped tunneling field-effect transistors (LTFETs) are used in biosensors due to their low subthreshold swing, off-state current, and power consumption.
Chen Chong, Hongxia Liu, Shulong Wang, Shupeng Chen, Haiwu Xie   +4 more
doaj   +1 more source

ZnO/graphene ambipolar transistor with low sub-threshold swing

Materials Research Express, 2021
We reported on enhanced device performance of ambipolar thin-film transistors (TFTs) with hybrid channel of Zinc oxide (ZnO) and multi-layer graphene (MLG), especially in reduced sub-threshold swing characteristics and increased carrier mobilities for ...
Byeong-Hyeok Kim, Sang-Hyun Hong, Jang-Won Kang   +2 more
doaj   +1 more source

Simulation of phonon-assisted band-to-band tunneling in carbon nanotube field-effect transistors [PDF]

, 2005
Electronic transport in a carbon nanotube (CNT) metal-oxide-semiconductor field effect transistor (MOSFET) is simulated using the non-equilibrium Green's functions method with the account of electron-phonon scattering.
Dmitri E. Nikonov, Landau L. D., M. P. Anantram, Mark S. Lundstrom, Siyuranga O. Koswatta   +4 more
core   +4 more sources

Characterization and Modeling of 28-nm Bulk CMOS Technology Down to 4.2 K

IEEE Journal of the Electron Devices Society, 2018
This paper presents an experimental investigation, compact modeling, and low-temperature physics-based modeling of a commercial 28-nm bulk CMOS technology operating at cryogenic temperatures. The physical and technological parameters are extracted at 300,
Arnout Beckers, Farzan Jazaeri, Christian Enz   +2 more
doaj   +1 more source

Improvement of Tunnel Field Effect Transistor Performance Using Auxiliary Gate and Retrograde Doping in the Channel [PDF]

Journal of Electrical and Computer Engineering Innovations, 2018
Background and Objectives: In this work, a dual workfunction gate-source pocket-retrograde doping-tunnel field effect transistor (DWG SP RD-TFET) is proposed and investigated.Methods: The dual workfunction gate-source pocket-retrograde doping-tunnel ...
M. Karbalaei, D. Dideban, N. Moezi
doaj   +1 more source