Results 81 to 90 of about 86,211 (240)
In this work, we demonstrated a robust 2D MoS2 based iontronic memtransistor of planar architecture operated under the influence of an electrical double layer with versatile performance and applications, including pinched hysteresis nature of transfer curve, analogue channel conductance tuning, low‐voltage operation, logic‐gate operation, classical ...
Puranjay Saha +2 more
wiley +1 more source
As CMOS technology approaches fundamental energy limits, new paradigms for low‐power information processing are required. Magnetic systems are attractive for their spin transport, yet current‐induced magnetization control is energy inefficient. Multiferroic heterostructures enable energy‐efficient electric field manipulation of magnetism.
Donghyeon Lee +3 more
wiley +1 more source
Gate engineering solutions to mitigate short channel effects in a 20 nm MOSFET
This work presents a promising approach to addressing scaling challenges in advanced MOSFET technology. It proposes a novel MOSFET structure designed to enhance electrical performance by introducing asymmetry in the gate dielectric thickness.
Ahmed S. Al-Jawadi +2 more
doaj +1 more source
High performance MoS2 TFT using graphene contact first process
An ohmic contact of graphene/MoS2 heterostructure is determined by using ultraviolet photoelectron spectroscopy (UPS). Since graphene shows a great potential to replace metal contact, a direct comparison of Cr/Au contact and graphene contact on the MoS2 ...
Chih-Shiang Chang Chien +5 more
doaj +1 more source
Analysis of Subthreshold Swing for Oxide Thickness and Doping Distribution in DGMOSFET [PDF]
In this paper, the relationship of potential and charge distribution in channel for double gate(DG) MOSFET has been derived from Poisson's equation using Gaussian function. The relationship of subthreshold swing and oxide thickness has been investigated according to variables of doping distribution using Gaussian function, i.e.
openaire +1 more source
Wafer‐Scale 3D Integration for High‐Density Multi‐Valued Neuromorphic Logic
Wafer‐scale 3D vertically integrated multi‐valued logic (MVL) circuits are realized by monolithically integrating a Te/IGZO heterojunction FET with an engineered Te pull‐up FET. Heterointerface‐mediated transport and optimized current matching enable stable ternary operation, while vertical stacking reduces circuit footprint and interconnect complexity,
Chang‐Hyeon Kim +5 more
wiley +1 more source
This study investigates the effects of thermal deposition rate on next‐generation p‐type amorphous oxide semiconductor SeTe–TeOx films. Deposition rate governs the chemical states, microstructure, and electrical characteristics of the films, resulting in tunable device properties.
Seongmo Kang +8 more
wiley +1 more source
Ferroelectric-Hf1-xZrxO2 FETs on silicon on insulator (SOI) are modeled and demonstrated with improvement on subthreshold swing (SS) and hysteresis (VT-shift), which is based on the capacitance matching concept.
Kuan-Ting Chen +14 more
doaj +1 more source
A virtual coaching environment for improving golf swing technique [PDF]
As a proficient golf swing is a key element of success in golf, many golfers make significant effort improving their stroke mechanics. In order to help enhance golfing performance, it is important to identify the performance determining factors within ...
Healy, Aoife +7 more
core +1 more source
A two-dimensional analytical model for short channel junctionless double-gate MOSFETs
A physics-based analytical model of electrostatic potential for short-channel junctionless double-gate MOSFETs (JLDGMTs) operated in the subthreshold regime is proposed, in which the full two-dimensional (2-D) Poisson’s equation is solved in channel ...
Chunsheng Jiang +3 more
doaj +1 more source

