Native GaN/GaO<sub>x</sub> Heterostructure Platform for Wafer-Scale Integration of High-Performance Complementary Transistors. [PDF]
Research (Wash D C)Liang J +7 more
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Quantum transport insights into layer-dependent behavior of Sub-1 nm MoS<sub>2</sub> transistors for advanced scaling. [PDF]
RSC AdvGhafoor M +6 more
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Machine learning-assisted design of carbon nanotube edge computing circuits for monolithic epidermal systems. [PDF]
Nat CommunLuo Z +10 more
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Strain-engineered Ge-source double-gate TFET with Si/SiGe/Si channel for low-power and THz frequency applications. [PDF]
Sci RepPrakash EB, Ray A, Bordoloi S.
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A machine-learning virtual source model for nanoscale transistors. [PDF]
Sci RepYang Q, Guo J.
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Controlling Vertical Diffusion with an Al<sub>2</sub>O<sub>3</sub> Back Interface Layer for Stable High-Performance InZnO TFTs. [PDF]
ACS OmegaLee SH +7 more
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Performance analysis of electrostatic and transport characteristics of underlap-engineered gate-all-around carbon nanotube (CNT) FETs for nanoelectronics circuitry applications. [PDF]
Sci RepBose SJ, Dhar RS, Hussein MI, Awwad F.
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Role of Si/dielectric interface traps on the reliability of tree-shaped complementary FETs for sub-3 nm technology nodes. [PDF]
Sci RepThanthri SS +4 more
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Solution-Processed High-k HfO<sub>2</sub> Gate Insulator for High-Performance Indium-Zinc-Oxide Thin-Film Transistors: Optimisation of Annealing Temperature and Insulator Thickness. [PDF]
Materials (Basel)Sairike J +4 more
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High performance and low leakage heterojunction 10 nm PZT NC-FinFET for low power application. [PDF]
Sci RepTripathi SL +3 more
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