Results 11 to 20 of about 13,751 (195)
This paper presents design the optimal channel dimensions for Silicon Fin Feld Effect Transistor (Si-FinFET) for improvement electrical characteristic of Si-FinFET depending on the electrical characteristics of the channel (I ON /I OFF , SS, VT, DIBL). The MuGFET simulation tool has been using to investigate the electrical characteristics of Si-FinFET.
Ahmed Mahmood +2 more
openaire +2 more sources
This study discusses the effects of working temperature on the GaP-FinFET structure. Using the Multi-Gate Field Effect Transistors (MuGFET) simulation tool, the properties of FinFET have been generated over a temperature range of T=0 °C to T=125 °C.
Yasir Hashim, Safwan Mawlood Hussein
openaire +2 more sources
We demonstrate that the shorter channel self-aligned top-gate (SA TG) coplanar indiumgallium- zinc oxide (IGZO) thin-film transistors (TFTs), with negative voltage applied to the back-gate, exhibit superior characteristics as driving transistors in ...
Chae-Eun Oh +9 more
doaj +2 more sources
Chip-Scale Graphene/IGZO Cold Source FET Array Enabling Sub-60 mV dec<sup>-1</sup> Super-Steep Subthreshold Swing. [PDF]
Super‐steep subthreshold swing (SS) below 60 mV dec−1 is demonstrated in graphene/IGZO cold source transistor arrays. Linear density of states with Dirac cone in graphene suppressed the Boltzmann thermal tail, while high‐k HfO2 dielectric having small body factor enhanced gating efficiency, hereby further reducing SS. An average SS of ≈46.4 mV dec−1 is
Oh S +13 more
europepmc +2 more sources
EFFECT OF FERRO ELECTRIC THICKNESS ON NEGATIVE CAPACITANCE FET (NCFET)
Conventional Field Effect Transistor (FET) are well known to require at least 60mV/decade at 300K change in the channel potential to change the current by a factor of 10. Due to this, 60mV/decade becomes the bottleneck of this day transistor.
Muhaimin Bin Mohd Hashim +2 more
doaj +1 more source
We reported three temperature regimes in subthreshold characteristics of 22-nm FD-SOI p-MOSFETs at operation ${T}\,\,=$ 300 K – 4.5 K. Subthreshold swing (SS)-plateau at 125 K – 50 K in combination with SS-linearity at ${T}\,\,=$ 300 K &
Yo-Ming Chang +4 more
doaj +1 more source
Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs
Energy efficiency in digital circuits is limited by the subthreshold swing (SS), which defines how abruptly a transistor switches between its ON and OFF-states.
Daniel S. Truesdell +3 more
doaj +1 more source
Effects of High-k Dielectrics with Metal Gate for Electrical Characteristics of SOI TRI-GATE FinFET Transistor [PDF]
The implementation of high-k gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components. From the simulation result; it was shown that HfO2 is the best dielectric material with metal gate TiN ...
Fatima Zohra Rahou +2 more
doaj +1 more source
Negative capacitance (NC) effects that could allow steep subthreshold swing (SS) in field-effect transistors (FETs) are still controversially discussed.
Xiuyan Li, Akira Toriumi
doaj +1 more source

