Results 41 to 50 of about 361,658 (190)
InAlN/Al/GaN high electron mobility transistors (HEMTs) directly on Si with dynamic threshold voltage for steep subthreshold slope (<60 mV/dec) are demonstrated in this study, and attributed to displacement charge transition effects.
Pin-Guang Chen +5 more
doaj +1 more source
On the relation between rf noise and subthreshold swing in InP HEMTs for cryogenic LNAs [PDF]
4 - 8 GHz low-noise amplifiers (LNAs) based on InP high electron mobility transistors (InP HEMTs) with different spacer thickness in the InAlAs-InGaAs heterostructure were fabricated and characterized at 5 K.
Li, Junjie +4 more
core
A single‐step laser annealing strategy is presented for dual‐gate a‐IGZO TFTs. The steep thermal gradient induces graded oxygen doping in the channel and simultaneous WOx removal at the contacts, enabling concurrent interface and contact engineering.
Sihyeon Kwon +9 more
wiley +1 more source
A scalable, solution‐processed WSe2/ZrO2‐x van der Waals heterostructure realizes a light‐induced field‐tunneling synapse (LIFTS) that activates exclusively under bright illumination, emulating the photopic adaptation of the human retina at the device level.
Kijeong Nam +10 more
wiley +1 more source
Combined UV–vis transmittance and wavelength‐dependent photo‐assisted DC I–V analyses reveal defect‐induced optical instability and a high density of deep donor‐like subgap traps in La‐doped SrSnO3. The resulting MOSFET achieves one of the highest on/off ratios reported for ABO3 perovskite devices, demonstrating the promise of stannate perovskites as ...
Sojin Jung +17 more
wiley +1 more source
In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity
Po-Jung Sung +6 more
doaj +1 more source
The perspective presents an integrated view of neuromorphic technologies, from device physics to real‐time applicability, while highlighting the necessity of full‐stack co‐optimization. By outlining practical hardware‐level strategies to exploit device behavior and mitigate non‐idealities, it shows pathways for building efficient, scalable, and ...
Kapil Bhardwaj +8 more
wiley +1 more source
Strained Silicon Single Nanowire Gate-All-Around TFETs with Optimized Tunneling Junctions
In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET) with gate-all-around (GAA) structure yielding Ion-current of 15 μA/μm at the supply voltage of Vdd = 0.5V with linear onset at low drain voltages.
Keyvan Narimani +4 more
doaj +1 more source
A dual‐timescale reservoir based on monolithically 3D (M3D)‐integrated CNT solid ion‐gated transistors is demonstrated. Tunable ionic dynamics and pulse‐engineered operation enable linear and symmetric synaptic updates. The M3D‐integrated array achieves robust temporal encoding and accurate classification of moving MNIST sequences, highlighting its ...
Haksoon Jung +9 more
wiley +1 more source
Barrier‐Assisted Plasma Doping for Spatially Selective Resistance Engineering in MoS2 Transistors
Barrier‐assisted NH3 plasma doping enables damage‐free, spatially selective carrier modulation in monolayer MoS2 transistors. An ultrathin pV3D3/Al2O3 protective‐dielectric stack acts as a chemical filter that allows NHx radicals to reach the MoS2 surface while blocking plasma damage. This process achieves a high electron concentration of 4.3 × 1013 cm−
Inseong Lee +15 more
wiley +1 more source

