Results 61 to 70 of about 1,298 (156)

Parametric Analysis of Spiking Neurons in 16 nm Fin Field‐Effect Transistor Technology

Advanced Intelligent Discovery, EarlyView.
Energy efficient computing has driven a shift toward brain‐inspired neuromorphic hardware. This study explores the design of three distinct silicon neuron topologies implemented in 16 nm fin field‐Effect transistor technology. While the Axon‐Hillock design achieves gigahertz throughput, its functional fragility persists. The Morris–Lecar model captures
Logan Larsh, Raiyan Siddique, Sarah S. Sharif, Yaser Mike Banad   +3 more
wiley   +1 more source

High Mobility Ge pMOSFETs with ZrO2 Dielectric: Impacts of Post Annealing

Nanoscale Research Letters, 2019
This paper investigates the impacts of post metal annealing (PMA) and post deposition annealing (PDA) on the electrical performance of Ge p-type metal-oxide-semiconductor field-effect transistors (pMOSFETs) with ZrO2 dielectric.
Huan Liu, Genquan Han, Yan Liu, Yue Hao
doaj   +1 more source

Tandem Neural Network Rapidly Solves Multivalued Inverse Problems: Application to Oxide‐Semiconductor Characterization

Advanced Intelligent Systems, EarlyView.
A tandem neural network directly solves the multivalued inverse problem of extracting semiconductor parameters from transistor measurements. Trained on only 1000 simulations, the network infers six material parameters (e.g., defect states, carrier concentration, mobility) in under 1 ms, demonstrating a broadly applicable framework for semiconductor ...
Masatoshi Kimura, Keisuke Ide, Kuan‐Ju Zhou, Atsushi Shimizu, Takayoshi Katase, Hidenori Hiramatsu, Kei Terayama, Hideo Hosono, Toshio Kamiya   +8 more
wiley   +1 more source

Ultralow subthreshold swing of 9 mV/dec for planar bulk GaAs MOSFETs at 4 K in quantum computing applications [PDF]

APL Electronic Devices
A record-low subthreshold swing (SS) of 9 mV/dec at 4 K has been achieved in planar bulk GaAs metal–oxide–semiconductor field-effect transistors (MOSFETs). The measured SS in our devices decreased with temperature, from 60 mV/dec at 300 K to 19 mV/dec at
L. B. Young, M. Hong, J. Kwo, M. J. Wang, H. W. Chang, K. M. Chen, B. Y. Chen, Y. T. Cheng, J. Liu, H. W. Wan, Y. H. G. Lin   +10 more
doaj   +1 more source

Ultralow‐Power Floating‐Gate InGaZnO Content‐Addressable Memory for Wearable Electrocardiogram Anomaly Detection

Advanced Intelligent Systems, EarlyView.
This study introduces a subthreshold in‐memory anomaly detection architecture for wearable ECG monitoring using floating‐gate IGZO content‐addressable memories on a flexible substrate. Area‐engineered coupling provides a high subthreshold slope, while subthreshold operation realizes intrinsic exponential distance evaluation and linear voltage sensing ...
Hyung‐Jun Noh, Sunyeol Bae, Yumin Yun, Junhyeong Park, Soo‐Yeon Lee   +4 more
wiley   +1 more source

Long‐Channel Effects in Randomly Oriented Carbon Nanotube Thin Film Transistors

Advanced Electronic Materials
Carbon nanotube (CNT) thin film transistors (TFTs) have demonstrated great potential for application in highly sensitive biosensors and large‐area electronics.
Hai‐Yang Liu, Panpan Zhang, Xianmao Cao, Yang Zhang, Jianping He, Maguang Zhu, Mengmeng Xiao, Zhiyong Zhang   +7 more
doaj   +1 more source

A Co‐Designed Implicit‐Reset Path PFD and Current Mismatch Compensated CP Enabling Sub‐0.5% Mismatch and Dead Zone‐Free for Low‐Spur PLLs

International Journal of Circuit Theory and Applications, EarlyView.
A co‐designed implicit‐reset phase‐frequency detector (PFD) and nonlinear amplifier‐assisted charge pump (CP) achieve dead zone‐free operation from 10 MHz to 4.7 GHz with < 0.5% current mismatch without calibration, enabling −80 dBc of reference spur and 0.50 ps of RMS jitter in a 180 nm of CMOS PLL.
A. Ghaemnia, Jincheng Yang, Xiaojiong Fei, G. Zhang   +3 more
wiley   +1 more source

Subthreshold Time‐Mode All‐Digital DLL With Built‐In Linearization

International Journal of Circuit Theory and Applications, EarlyView.
This paper presents a subthreshold time‐mode all‐digital delay‐locked loop (DLL) for low‐frequency clock generation. The large and tunable delay of the DLL is obtained using a static inverter delay line whose supply voltage is in the vicinity of 100 mV and adjustable by varying supply voltage. Phase error is processed by a time‐mode proportional block (
Fei Yuan, Wenhao Wu, Yushi Zhou
wiley   +1 more source

Low‐Dimensional Materials and Van Der Waals Heterostructures for Energy Application: A Comprehensive Review

ENERGY &ENVIRONMENTAL MATERIALS, EarlyView.
Low‐dimensional materials (0D, 1D, and 2D) exhibit unique electronic and physicochemical properties, enabling advanced nanoelectronic and optoelectronic devices. Mixed‐dimensional heterostructures combine these materials to enhance functionality.
Qaisar Alam, Sajjad Ali, Pir Muhammad Ismail, ABM Sharif Hossain   +3 more
wiley   +1 more source

Material design strategies for flexible n‐type polymer semiconductors

FlexMat, EarlyView.
This Perspective surveys recent progress in flexible n‐type polymer semiconductors, emphasizing the interplay between molecular design and microstructure control. It outlines strategies including backbone and side‐chain engineering, multilevel microstructure optimization, to maintain charge‐transport pathways under mechanical deformation.
Xiao‐Yan Zhang, Yang‐Yang Zhou, Jie‐Yu Wang, Jian Pei, Ze‐Fan Yao   +4 more
wiley   +1 more source