Results 31 to 40 of about 1,298 (156)
InAlN/Al/GaN high electron mobility transistors (HEMTs) directly on Si with dynamic threshold voltage for steep subthreshold slope (<60 mV/dec) are demonstrated in this study, and attributed to displacement charge transition effects.
Pin-Guang Chen +5 more
doaj +1 more source
Oxygen‐tunnel (OT) indium tin oxide (ITO) vertical channel transistors (VCTs) enable reliable, high‐density gain‐cell memory for monolithic 3D integration. A sandwiched SiN/SiO2/SiN OT stack selectively regulates oxygen transport, suppressing parasitic electrode oxidation while stabilizing channel oxygen vacancies, thereby suppressing carrier injection
Hyeonho Gu +17 more
wiley +1 more source
Wafer‐scale two‐dimensioanl In2Se3 oxidized into InOx on sodium‐embedded beta‐alumina enables multifunctional reconfigurable electronics. Sodium ions accumulate within distinct spatial distribution under drain‐controlle and gate‐controlled operation. Drain‐control operation gives controllability of ultraviolet‐driven optoelectronic synaptic conductance
Jinhong Min +13 more
wiley +1 more source
In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity
Po-Jung Sung +6 more
doaj +1 more source
Direct channel implantation of B and BF2 ions was employed to fabricate amorphous IGZO TFTs with improved electrical and stability properties. B and BF2 implantation modulate oxygen vacancies within the IGZO channel. The field‐effect mobility of ion‐implanted IGZO TFTs was enhanced as compared to pristine IGZO TFTs.
Beom Soo Kim +9 more
wiley +1 more source
A single‐step laser annealing strategy is presented for dual‐gate a‐IGZO TFTs. The steep thermal gradient induces graded oxygen doping in the channel and simultaneous WOx removal at the contacts, enabling concurrent interface and contact engineering.
Sihyeon Kwon +9 more
wiley +1 more source
Strained Silicon Single Nanowire Gate-All-Around TFETs with Optimized Tunneling Junctions
In this work, we demonstrate a strained Si single nanowire tunnel field effect transistor (TFET) with gate-all-around (GAA) structure yielding Ion-current of 15 μA/μm at the supply voltage of Vdd = 0.5V with linear onset at low drain voltages.
Keyvan Narimani +4 more
doaj +1 more source
Tunable Complementary Doping Strategy Enables High‐Performance Homo‐Channel CMOS in Monolayer WSe2
Polarity‐selective modulation enables a homo‐channel WSe2 CMOS platform from a single 2D semiconductor. MoOx and AlN tune WSe2 toward p‐ and n‐type operation, respectively, yielding complementary FETs and inverters with balanced switching, high voltage gain, low static power, and promising scalability for 2D logic integration.
Kuan‐Hsiang Chiu +7 more
wiley +1 more source
The perspective presents an integrated view of neuromorphic technologies, from device physics to real‐time applicability, while highlighting the necessity of full‐stack co‐optimization. By outlining practical hardware‐level strategies to exploit device behavior and mitigate non‐idealities, it shows pathways for building efficient, scalable, and ...
Kapil Bhardwaj +8 more
wiley +1 more source
The main challenge for tunnel field-effect transistors (TFETs) is achieving high on-current (Ion) and low subthreshold swing (SS) with reasonable ambipolar characteristics.
Garam Kim +3 more
doaj +1 more source

