Results 11 to 20 of about 1,273 (146)
EFFECT OF FERRO ELECTRIC THICKNESS ON NEGATIVE CAPACITANCE FET (NCFET)
Conventional Field Effect Transistor (FET) are well known to require at least 60mV/decade at 300K change in the channel potential to change the current by a factor of 10. Due to this, 60mV/decade becomes the bottleneck of this day transistor.
Muhaimin Bin Mohd Hashim +2 more
doaj +1 more source
We reported three temperature regimes in subthreshold characteristics of 22-nm FD-SOI p-MOSFETs at operation ${T}\,\,=$ 300 K – 4.5 K. Subthreshold swing (SS)-plateau at 125 K – 50 K in combination with SS-linearity at ${T}\,\,=$ 300 K &
Yo-Ming Chang +4 more
doaj +1 more source
Minimum-Energy Digital Computing With Steep Subthreshold Swing Tunnel FETs
Energy efficiency in digital circuits is limited by the subthreshold swing (SS), which defines how abruptly a transistor switches between its ON and OFF-states.
Daniel S. Truesdell +3 more
doaj +1 more source
Effects of High-k Dielectrics with Metal Gate for Electrical Characteristics of SOI TRI-GATE FinFET Transistor [PDF]
The implementation of high-k gate dielectrics is one of several strategies developed to allow further miniaturization of microelectronic components. From the simulation result; it was shown that HfO2 is the best dielectric material with metal gate TiN ...
Fatima Zohra Rahou +2 more
doaj +1 more source
Negative capacitance (NC) effects that could allow steep subthreshold swing (SS) in field-effect transistors (FETs) are still controversially discussed.
Xiuyan Li, Akira Toriumi
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A gate-normal hetero-gate-dielectric (GHG) tunnel field-effect transistor (TFET) and the guidelines for its design are proposed. The introduction of the HG structure into gate-normal TFETs improves device performance by lowering subthreshold swing (SS ...
Jang Woo Lee, Woo Young Choi
doaj +1 more source
Ferroelectric-Hf1-xZrxO2 FETs on silicon on insulator (SOI) are modeled and demonstrated with improvement on subthreshold swing (SS) and hysteresis (VT-shift), which is based on the capacitance matching concept.
Kuan-Ting Chen +14 more
doaj +1 more source
In this paper, we propose an inductive line tunneling FET using Epitaxial Tunnel Layer with Ge-Source and Charge Enhancement Insulation (CEI ETL GS-iTFET).
Jyi-Tsong Lin, Yen-Chen Chang
doaj +1 more source
This paper presents design the optimal channel dimensions for Silicon Fin Feld Effect Transistor (Si-FinFET) for improvement electrical characteristic of Si-FinFET depending on the electrical characteristics of the channel (I ON /I OFF , SS, VT, DIBL). The MuGFET simulation tool has been using to investigate the electrical characteristics of Si-FinFET.
Ahmed Mahmood +2 more
openaire +1 more source
GaN Nanotube FET With Embedded Gate for High Performance, Low Power Applications
On the road of CMOS device continuously scaling, there are lots of challenges regarding the device structure and material engineering. GaN channel has recently been used in MOSFETs and achieved excellent performance.
Ke Han +4 more
doaj +1 more source

