Results 201 to 210 of about 2,393 (257)

Another design of the successive approximation register for A/D converters

Proceedings of the IEEE, 1979
An alternative design of the successive approximation register is proposed. The design eliminates the dual flip-flop outputs of previous designs.
C K Yuen
exaly   +2 more sources

Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs

ACM Transactions on Design Automation of Electronic Systems, 2015
The performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold circuits, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can result from two sources of errors: random mismatch and systematic mismatch.
Chien Chih Huang, Jwu-E Chen, Chin-Long Wey   +2 more
exaly   +2 more sources

A 90 nm low-power successive approximation register for A/D conversions

2011 12th International Symposium on Quality Electronic Design, 2011
A novel low-power successive approximation register is proposed. The new register is based on gating the clock when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications.
Mohamed O. Shaker, Magdy A. Bayoumi
exaly   +2 more sources

The Development of Successive Approximation Register for SAR ADC

2024 Conference of Young Researchers in Electrical and Electronic Engineering (ElCon)
Kristina D. Pepelyaeva, Mikhail A. Bellavin   +1 more
exaly   +2 more sources

Successive Approximation Register TDC in Time-Mode Signal Processing

2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021
An 8-bit time-mode pseudo-differential successive approximation register time-to-digital converter (SAR TDC) is presented. The TDC achieves a high resolution and a better power/area efficiency using a pair of 16-stage pre-skewed delay line for 4-bit coarse digital-to-time conversion and a pair of digital time interpolators for 4-bit fine digital-to ...
Daniel Junehee Lee, Fei Yuan 0005, Yushi Zhou   +2 more
openaire   +1 more source

A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS

Journal of Circuits, Systems and Computers, 2014
A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications.
Mohamed O. Shaker, Magdy A. Bayoumi
openaire   +1 more source

Low power design of successive approximation registers

2013 21st Iranian Conference on Electrical Engineering (ICEE), 2013
This paper presents low power design methods for successive approximation registers (SARs) that may serve as the digital part of a successive approximation analog to digital converter (SA-ADC). The SAR is designed in 130nm technology in the sub-threshold region to meet the goal of reduced power consumption.
openaire   +1 more source

An energy-efficient successive approximation register analog to digital converter in 180nm

2010 IEEE Asia Pacific Conference on Circuits and Systems, 2010
This paper presents an analog-to-digital converter using state-of-the-art techniques in 180nm process. Making use of charge sharing, asynchronous logic circuitry, scaled digital voltage supply and a novel sampling scheme, this ADC achieves a figure of merit (FOM) of 45fJ per conversion step in simulations.
Taimur Gibran R. Kuntz, Saeid Nooshabadi
openaire   +1 more source

A high-resolution synchronous mirror delay using successive approximation register

IEEE Journal of Solid-State Circuits, 2004
A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD .
Sung, K, Kim, LS Kim, Lee-Sup
openaire   +2 more sources

Statistical modeling of capacitor mismatch effects for successive approximation register ADCs

2011 International SoC Design Conference, 2011
This paper presents an efficient modeling method for the effects of capacitor mismatches in SAR ADCs. As the capacitor mismatch can severely degrade accuracy, it is necessary to determine the limitation of the resolution. We statistically analyze the resolution of the SAR ADCs considering both the traditional approach and the proposed advanced analysis,
Youngjoo Lee, Jinook Song, In-Cheol Park
openaire   +1 more source