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A successive approximation register for analog-to-BCD conversion
Proceedings of the IEEE, 1982It is shown that by adding a few OR gates to a previous design of the successive approximation register, we can use it in direct analog-to-BCD conversion.
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Another design of the successive approximation register for A/D converters
Proceedings of the IEEE, 1979An alternative design of the successive approximation register is proposed. The design eliminates the dual flip-flop outputs of previous designs.
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Successive Approximation Register TDC in Time-Mode Signal Processing
2021 IEEE International Midwest Symposium on Circuits and Systems (MWSCAS), 2021An 8-bit time-mode pseudo-differential successive approximation register time-to-digital converter (SAR TDC) is presented. The TDC achieves a high resolution and a better power/area efficiency using a pair of 16-stage pre-skewed delay line for 4-bit coarse digital-to-time conversion and a pair of digital time interpolators for 4-bit fine digital-to ...
Daniel Junehee Lee, Fei Yuan, Yushi Zhou
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Successive approximation register ADC single event effects protection and evaluation
Journal of Instrumentation, 2022Abstract This work analyses seven different alternatives to implement an ADC based on the successive approximation register (SAR) architecture. The influence of the encoding is taken into account while evaluating the importance of its reset approach. Different protection strategies against single event upsets are addressed, including the
B. Sanches +3 more
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Radiation-hardened successive approximation register analog-to-digital converter
2020 International Conference on Electronics, Information, and Communication (ICEIC), 2020Radiation-hardened-by-design (RHBD) techniques have kept evolving for the past decades to satisfy the requirements of irradiating environments; however, the possibilities of severe nuclear accidents still remain. To prevent and be well prepared for extreme events, advanced circuit designs reliable under harsh conditions are necessary.
Seungho Jhung +5 more
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An 8-bit 35-MS/s successive approximation register ADC
2015 IEEE International Conference on Progress in Informatics and Computing (PIC), 2015An 8-bit 35-MS/s successive approximation register analog-to-digital converter implemented in 0.18µm CMOS process is presented in this paper. To reduce the total power consumption, split capacitor DAC structure coupled with Merged Capacitor Switching (MCS) technique is used.
null Xiucheng Zhou +2 more
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Performance-Driven Unit-Capacitor Placement of Successive-Approximation-Register ADCs
ACM Transactions on Design Automation of Electronic Systems, 2015The performance of many switched-capacitor analog integrated circuits, such as analog-to-digital converters (ADCs) and sample and hold circuits, is directly related to their accurate capacitance ratios. In general, capacitor mismatch can result from two sources of errors: random mismatch and systematic mismatch.
Chien-Chih Huang +3 more
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Low power design of successive approximation registers
2013 21st Iranian Conference on Electrical Engineering (ICEE), 2013This paper presents low power design methods for successive approximation registers (SARs) that may serve as the digital part of a successive approximation analog to digital converter (SA-ADC). The SAR is designed in 130nm technology in the sub-threshold region to meet the goal of reduced power consumption.
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A CLOCK GATED SUCCESSIVE APPROXIMATION REGISTER FOR A/D CONVERSIONS
Journal of Circuits, Systems and Computers, 2014A novel low power clock gated successive approximation register (SAR) is proposed. The new register is based on gating the clock signal when there is no data switching activity. It operates with fewer transistors and no redundant transitions which makes it suitable for low power applications.
MOHAMED O. SHAKER, MAGDY A. BAYOUMI
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A high-resolution synchronous mirror delay using successive approximation register
IEEE Journal of Solid-State Circuits, 2004A high-resolution synchronous mirror delay (SMD) is proposed in order to reduce the clock skew between the external clock and the internal clock of a chip. The proposed SMD reduces the clock skew in two steps. Coarse locking is achieved by the conventional SMD .
Sung, K, Kim, LS Kim, Lee-Sup
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