Results 251 to 260 of about 48,643 (286)

Design of time reduction for successive approximation register A/D converter

2015 7th International Conference on Information Technology and Electrical Engineering (ICITEE), 2015
Acting as the gateway between the "real world" analog signal and digital signal, data converters have become a critical element of modern electronic devices. High-performance applications have put a particular emphasis on high-speed data conversion converters.
Mon Mon Thin, Myo Min Than
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Statistical modeling of capacitor mismatch effects for successive approximation register ADCs

2011 International SoC Design Conference, 2011
This paper presents an efficient modeling method for the effects of capacitor mismatches in SAR ADCs. As the capacitor mismatch can severely degrade accuracy, it is necessary to determine the limitation of the resolution. We statistically analyze the resolution of the SAR ADCs considering both the traditional approach and the proposed advanced analysis,
YoungJoo Lee, Jinook Song, In-Cheol Park
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An energy-efficient successive approximation register analog to digital converter in 180nm

2010 IEEE Asia Pacific Conference on Circuits and Systems, 2010
This paper presents an analog-to-digital converter using state-of-the-art techniques in 180nm process. Making use of charge sharing, asynchronous logic circuitry, scaled digital voltage supply and a novel sampling scheme, this ADC achieves a figure of merit (FOM) of 45fJ per conversion step in simulations.
Taimur Gibran Rabuske Kuntz, Saeid Nooshabadi   +1 more
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Interleaving of Successive-Approximation Register ADCs in Deep Sub-Micron CMOS Technology

2013
This paper reviews recent developments of interleaved Successive Approximation Analog-to-Digital converters (SAR) in deep sub-micron CMOS technologies. The discussion covers design tradeoffs and degrees of freedom related to the impact of extensive interleaving with many SAR units on bandwidth, noise, linearity, and spurious performance.
Doris, K., Janssen, E.J.G., Lin, Y., Zanikopoulos, A., Murroni, A.   +4 more
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A Successive Approximation Register Analog to Digital Converter for Low Power Applications

Journal of Computational and Theoretical Nanoscience, 2020
In recent years and continuing, widespread research work is carried out on medical implantable devices placed inside the human body. The essential and vital electronic circuit in implantable devices is the Analog to Digital Converter (ADC). The essential requirements in these applications such as long battery life-time, low power consumption and less ...
Yahya Mohammed Ali Al-Naamani, K. Lokesh Krishna, A. M. Guna Sekhar   +2 more
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A Novel Successive Approximation Register ADC Based on Vernier Caliper Design

2014
This study presents a new method for the design of a N-bit successive approximation register (SAR) analog-to-digital converter (ADC) which employs the main-scale Vernier-scale characteristics of a Vernier caliper. The proposed design is similar to a half-SAR design where the main half-SAR ADCs the N/2 most significant bits (MSBs) from comparisons of ...
Chih-Feng Huang, Chien-Yuan Liu, Yi-Chin Chen   +2 more
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10-bit 47.57μW Power Efficient Successive Approximation Register ADC with High Speed

2018 3rd IEEE International Conference on Recent Trends in Electronics, Information & Communication Technology (RTEICT), 2018
A 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) prototype is presented in this work and simulations are performed using Cadence Spectre on 16 nm technology. This architecture consists of a bulk driven rail to rail comparator and split binary weighted capacitive Digital to Analog Converter (DAC).
Sapna Devi, Shweta Meena, Sanjeeb Mishra
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Integrated successive approximation register analog-to-digital converter for healthcare systems applications

2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014
This paper presents low-power radio-frequency identification (RFID) technology for intelligent healthcare systems. The proposed a 1-V 8-bit successive approximation register (SAR) analog-to-digital converter (ADC) implemented in TSMC 0.18-um CMOS process is presented.
Wen-Cheng Lai, Jhin-Fang Huang, Ting Ye, Chieh Wen Shih   +3 more
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A novel comparator-assisted switching strategy used in Successive Approximation Register ADC

2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012
Recently Successive Approximation Register (SAR) ADC is more and more important in low power and small layout area application field such as implantable medical system. SAR ADC has moderate speed, moderate resolution and very low power characteristics. Some researchers have focused on improving the efficiency and layout area of SAR ADC.
Yan-jia Ke, Xiao-bo Wu, Meng-lian Zhao
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Low-Power Circuit Techniques for Charge-Scaling Successive Approximation Register ADC Design

Journal of Low Power Electronics, 2010
Charge-scaling (CS) successive approximation register (SAR) ADC's are widely used in low-power electronics design. A significant portion of CS-SAR ADC power consumption is due to charging the CS capacitor array. This paper presents circuit techniques to reduce the voltage swing, and hence the power dissipation, of the CS capacitor array during ADC ...
Mallik Kandala, Haibo Wang
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