Impact of drain and source engineering on dual metal InAs-GaSb VTFETs with high-K gate stack design. [PDF]
Saravanan M +3 more
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Advances in High-Voltage Power Electronics Using Ga<sub>2</sub>O<sub>3</sub>-Based HEMT: Modeling. [PDF]
Alhasani R +4 more
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Silvaco TCAD modeling, optical simulation, and optimization for high-current perovskite and u-CIGS tandem solar cells with efficiencies above 30. [PDF]
Mosalanezhad R +2 more
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Design and performance analysis of a vertically stacked gate-all-around nanosheet FET with embedded nanocavity for biosensing applications. [PDF]
Prasanna RL +3 more
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Characteristics Prediction and Optimization of GaN CAVET Using a Novel Physics-Guided Machine Learning Method. [PDF]
Wu W, Wang J, Su J, Chen Z, Yu Z.
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The Modeling of a Single-Electron Bipolar Avalanche Transistor in 150 nm CMOS. [PDF]
Boughedda A +6 more
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Device to Circuit Co-Design Utilizing High-Performance PEALD Indium-Gallium-Zinc Oxide Thin-Film Transistor Enabling Technology Node Scaling in Monolithic 3D Systems. [PDF]
Wang W +11 more
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Polarization Engineered Design for Normally-Off, Higher Drain Current and Higher Breakdown Voltage Gan-Based MOS-HEMT. [PDF]
Omar A, Loan SA.
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Enabling scalable ferroelectric-based future generation vertical NAND flash with bonding-friendly architecture: strategies for erase and disturb optimization. [PDF]
Song I, Kim J, Lee S, Myeong I.
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