Results 201 to 210 of about 784 (245)

Synthesis of Balanced Ternary Reversible Logic Circuit

2013 IEEE 43rd International Symposium on Multiple-Valued Logic, 2013
Ternary logic synthesis has a significant role to realize multi-input ternary logic functions. Balanced ternary logic that contains three states as -1, 0 and 1 has substantial advantage over standard ternary logic containing the logic states as 0, 1 and 2.
B. Mondal, P. Sarkar, P. K. Saha, S. Chakraborty   +3 more
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Design of ternary logic circuits using CNTFET

2018 International Symposium on Devices, Circuits and Systems (ISDCS), 2018
The work in this paper presents the design of ternary logic circuits using MOSFET-like carbon nanotube field effect transistor (CNTFET). The ternary logic is one of multivalued logic circuits which is the best substitute for traditional binary logic because of its low power consumption and low power delay product (PDP) resulting from reduced complexity
Debaprasad Das, Anirban Banerjee, Vikash Prasad   +2 more
openaire   +1 more source

Functionalized Organic Material Platform for Realization of Ternary Logic Circuit

ACS Applied Materials & Interfaces, 2020
Negative differential resistance/transconductance (NDR/NDT) has been attracting significant attention as a key functionality in the development of multivalued logic (MVL) systems that can overcome the limits of conventional binary logic devices. A high peak-to-valley current ratio (PVCR) and more than double-peak transfer characteristics are required ...
Jaeho Jeon, Min Je Kim, Gicheol Shin, Myeongjae Lee, Young Jae Kim, BongSoo Kim, Yoonmyung Lee, Jeong Ho Cho, Sungjoo Lee   +8 more
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Design of encoder for ternary logic circuits

2012 Asia Pacific Conference on Postgraduate Research in Microelectronics and Electronics, 2012
Ternary logic is a promising alternative to conventional binary logic, since it is possible to achieve simplicity and energy efficiency due to the reduced circuit overhead. In this paper a design of ternary arithmetic logic circuits based on Carbon Nanotube Field Effect Transistors (CNFETs) is presented.
P Viswa Saidutt, V Srinivas, P Sai Phaneendra, N Moorthy Muthukrishnan   +3 more
openaire   +1 more source

Swhched-current CMOS ternary logic circuits

International Journal of Electronics, 1995
Abstract A new switched-current CMOS ternary logic family is presented. Circuit descriptions of the basic gates (inverters, NAND, and NOR) are presented and their performance characteristics are evaluated using SPICE simulations. The results obtained indicate that the proposed circuits have good noise margins of about 15% of the power supply voltage ...
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Pseudo-random testing of CMOS ternary logic circuits

[1988] Proceedings. The Eighteenth International Symposium on Multiple-Valued Logic, 1988
Two structures that can be used to test ternary logic VLSI circuits are described and compared: the ternary BILBO (built-in logic block observer) and the ternary CALBO (cellular automaton logic block observer). These structures can be used to generate pseudorandom test patterns and signatures.
C. Rozon, H.T. Mouftah
openaire   +1 more source

A Review on Fundamentals of Ternary Reversible Logic Circuits

2020 International Conference on Computational Performance Evaluation (ComPE), 2020
One of the main motivations for using ternary logic systems is the amount of information per circuit line is higher as compared to the corresponding binary logic representation, thereby leading to more compact circuit realizations. This is particularly attractive for quantum computing as qutrits are expensive resources and minimizing their number is ...
P. Mercy Nesa Rani, Phrangboklang Lyngton Thangkhiew   +1 more
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A novel ternary logic circuit using Josephson junction

IEEE Transactions on Magnetics, 1989
A novel Josephson complementary ternary logic (JCTL) circuit is described. This fundamental circuit is based on the combination of two SQUIDs (superconducting quantum interference devices), one of which is switched in the positive direction and the other in the negative direction.
M. Morisue, K. Oochi, M. Nishizawa
openaire   +1 more source

Efficient Ternary Logic Circuits Optimized by Ternary Arithmetic Algorithms

IEEE Transactions on Emerging Topics in Computing
Multi-valued logic (MVL) circuits, especially the ternary logic circuits, have attracted great attention in recent years due to their higher information density than binary logic systems. However, the basic construction method for MVL circuit standard cells and the CMOS fabrication possibility/compatibility issues are still to be addressed.
Zhao, Guangchao, Zeng, Zhiwei, Wang, Xingli, Qoutb, Abdelrahman, Coquet, Philippe, Friedman, Eby, Tay, Beng Kang, Huang, Mingqiang   +7 more
openaire   +1 more source

Design of Quad-Edge-Triggered Sequential Logic Circuits for Ternary Logic

2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019
We propose a quad-edge-triggered flip-flop which captures and propagates a ternary data signal at four-edges of a ternary clock signal. The proposed circuit uses carbon nanotube FETs and consists of four types of logic gate: ternary clock driver, standard ternary inverter, binary inverter, and transmission gate.
Sunmean Kim, Sung-Yun Lee, Sunghye Park, Seokhyeong Kang   +3 more
openaire   +1 more source