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Hafnium-Based Ferroelectric Post-Moore Electronics: Device Physics, Integration Architectures, and Neuromorphic System Implementation. [PDF]
Chen X, Wang Z, Meng J, Wang T.
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Enhanced CPU Design for SDN Controller. [PDF]
Bazzi HS +4 more
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From undruggable to degradable: A deep learning-enabled framework for precision orthopaedic protein degradation. [PDF]
Zhang L, Wang Y, Wang D, Ma J.
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Self-checking binary logic systems using ternary logic circuits
Canadian Electrical Engineering Journal, 1984The present status of multivalued logic is highlighted in a Canadian context. A particular example is given of the use of ternary circuits in the solution of the problem of testability of binary logic, through the introduction of a new concept called 2-of-3-valued logic.
M. Hu, K. C. Smith
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Binary/Ternary Logic Applications for Systems Programming and Reversible Computing
2019 SoutheastCon, 2019A binary/ternary system differs from a pure or standard ternary system by emphasizing the interplay between binary and ternary data. In this paper we use binary/ternary constructs in three ways: first, to efficiently construct reversible two-valued binary gates, second, to define machine-level operations that may be used in systems or low-level ...
Waleed K Al-Assadi
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Advanced Materials Research, 2012
Spiking neural P systems are a class of distributed and parallel computing models inspired by P systems and spiking neural networks.Spiking neural P system with anti-spikes can encode the balanced ternary three digits in a natural way using three states called anti-spikes, no-input and spikes.
Xiao Ping Fan, Fan Xiao Ping
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Spiking neural P systems are a class of distributed and parallel computing models inspired by P systems and spiking neural networks.Spiking neural P system with anti-spikes can encode the balanced ternary three digits in a natural way using three states called anti-spikes, no-input and spikes.
Xiao Ping Fan, Fan Xiao Ping
exaly +2 more sources
Design of an asynchronous digital system with B-ternary logic
Proceedings 1997 27th International Symposium on Multiple- Valued Logic, 2002Some of the recent digital systems have a serious clock skew problem which comes from huge hardware implementations and high speed operations in VLSI's. To overcome this problem, clock distribution techniques and more notably, asynchronous system design methodologies, have been investigated.
Yasunori Nagata, Masao Mukaidono
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Logic synthesis of controllers for B-ternary asynchronous systems
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000), 2002Asynchronous digital circuits and self-timed circuits are receiving attention due to the rapid development of VLSI technology and the difficulty of global clock distribution. In addition, an asynchronous system consumes lower power because unused parts of the system are deactivated, and the computational time is average-case instead of worst-case.
Yasunori Nagata +2 more
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A Lamb wave device for a communication system with ternary logic
Proceedings of the IEEE, 1980A new type of Lamb wave device for signal processing with ternary logic is presented. The transducer consists of a group of three electrodes deposited on two surfaces of a thin piezoelectric substrate. One is on the bottom surface as a common earth electrode. The other two are interdigital electrodes on the top surface.
K. Toda, Y. Yamashita
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Ternary simulation of digital systems in CAD programmable logic
Modern Problems of Radio Engineering, Telecommunications and Computer Science (IEEE Cat. No.02EX542), 2003Here is considered the problems of interpretative and compilation simulation of digital systems. Investigated the influence of logic transformation of gate models. Offered procedures, which modify the method of ternary simulation and avoid incorrect execution of direct implication in the cubic coverage of the given gate structure. Here is some examples,
A.S. Shkil, V.V. Pobezenko, I.Y. Sysenko
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