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Binary/Ternary Logic Applications for Systems Programming and Reversible Computing
2019 SoutheastCon, 2019A binary/ternary system differs from a pure or standard ternary system by emphasizing the interplay between binary and ternary data. In this paper we use binary/ternary constructs in three ways: first, to efficiently construct reversible two-valued binary gates, second, to define machine-level operations that may be used in systems or low-level ...
Lucius T. Schoenbaum +1 more
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Exploration of Ternary Logic Using T-CMOS for Circuit-Level Design [PDF]
IEEE Transactions on Circuits and Systems I: Regular Papers, 2023 The predicted end of scaling and the exponential increase of user data in the era of the connected world are asking whether the current binary systems in CMOS can successfully provide solutions to the expected challenges.
Jonghyun Ko +2 more
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Design of an asynchronous digital system with B-ternary logic
Proceedings 1997 27th International Symposium on Multiple- Valued Logic, 2002Some of the recent digital systems have a serious clock skew problem which comes from huge hardware implementations and high speed operations in VLSI's. To overcome this problem, clock distribution techniques and more notably, asynchronous system design methodologies, have been investigated.
Yasunori Nagata, Masao Mukaidono
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Logic synthesis of controllers for B-ternary asynchronous systems
Proceedings 30th IEEE International Symposium on Multiple-Valued Logic (ISMVL 2000), 2002Asynchronous digital circuits and self-timed circuits are receiving attention due to the rapid development of VLSI technology and the difficulty of global clock distribution. In addition, an asynchronous system consumes lower power because unused parts of the system are deactivated, and the computational time is average-case instead of worst-case.
Yasunori Nagata +2 more
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A Lamb wave device for a communication system with ternary logic
Proceedings of the IEEE, 1980A new type of Lamb wave device for signal processing with ternary logic is presented. The transducer consists of a group of three electrodes deposited on two surfaces of a thin piezoelectric substrate. One is on the bottom surface as a common earth electrode. The other two are interdigital electrodes on the top surface.
K. Toda, Y. Yamashita
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Ternary simulation of digital systems in CAD programmable logic
Modern Problems of Radio Engineering, Telecommunications and Computer Science (IEEE Cat. No.02EX542), 2003Here is considered the problems of interpretative and compilation simulation of digital systems. Investigated the influence of logic transformation of gate models. Offered procedures, which modify the method of ternary simulation and avoid incorrect execution of direct implication in the cubic coverage of the given gate structure. Here is some examples,
A.S. Shkil, V.V. Pobezenko, I.Y. Sysenko
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Experimental system of ternary logic optical computer with reconfigurability
SPIE Proceedings, 2009An experimental system of a ternary logic optical computer, including its working principle, architecture and main components, is proposed. The main object of this paper is to give readers a holistic understanding of the ternary optical computer. This experimental system, which fully exploits the parallelism of optics, can have huge data bus width ...
Zhang-Yi Shen, Yi Jin, Jun-Jie Peng
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On constructing intellectual systems in ternary logic
Programming and Computer Software, 2014The paper shows that it is possible to develop an intelligent system on a production knowledge model using three-valued logic, which operates with the states "truth, false, possible". A method is proposed for constructing intelligent systems that are free from contradictions and are capable of not only extracting facts but also explaining what facts ...
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A redundant binary adder using a symmetric ternary logic system
International Journal of Electronics, 1993A construction method is described for a fast parallel adder by using a redundant binary code (RBC). The RBC used has a fixed radix 2 and a digit set {−1,0,1}. The fast parallel adder is composed of ternary-valued CMOS gate networks, which are used in the symmetric ternary logic system, and its construction can be optimized with them.
SHINSAKU HIGASHI +3 more
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Ternary Logic Signals Transmission Based on a Unified Chaotic System
2006 International Conference on Communications, Circuits and Systems, 2006In this paper, we present a method for transmitting ternary logic digital signals based on chaos masking, using a new unified chaotic system. The unified chaotic system is in the form of a general Lorenz system, which can generate the dynamics of Lorenz system, Chen system or Lu system, controlled by a simple analog switch.
Wenbo Liu +2 more
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