Results 261 to 270 of about 2,729 (294)

Simulation of Ternary CMOS Schemes for Many-Valued Logic Systems

2019 IEEE 31st International Conference on Microelectronics (MIEL), 2019
Of interest is the possibility of implementing many-valued logic systems using traditional CMOS technologies. We considered an example of the implementation of three-valued logic elements based on symmetric 3vL logic using the values {-,0,+}, {-1.0, + 1}, {1,0,1}, {1,0,1} etc.
A. A. Krasnyuk, A. G. Prozorova
openaire   +1 more source

A P-ternary threshold element network-an application of ternary logic to a neural system treating ambiguity

Proceedings. The Nineteenth International Symposium on Multiple-Valued Logic, 2003
An application of ternary logic to a neural system treating ambiguity is considered. A method to find a threshold function (a learning method) is proposed. Ternary logic functions with no information loss concerning ambiguity, called P-functions, are introduced.
Y. Yamamoto, M. Mukaidono
openaire   +1 more source

Comparative Analysis of Crosstalk Effects in Dielectric Inserted Horizontal andVertical Multi-layer GNR Interconnects for Ternary Logic System

ECS Journal of Solid State Science and Technology, 2022
In this work, the performance of copper (Cu), dielectric inserted horizontal graphene nanoribbon (Di-HGNR) interconnect and dielectric inserted vertical graphene nanoribbon (Di-VGNR) interconnects are investigated using active shielding and passive shielding techniques.
Gurijala Deepthi, Madhavi Tatineni
openaire   +1 more source

Designing Unconventional Molecular Ternary INHIBIT Logic Gate and Crafting Multifunctional Molecular Logic Systems

The Journal of Physical Chemistry B
The paper describes an improved method for building flexible interswitchable logic gates such as rare-type molecular ternary INHIBIT and combinational logic circuits using a specially designed pyridine-end oligo-p-phenylenevinylene compound featuring alkyl substituents (-C16H33) in a THF medium.
Monaj Karar, Harshal V. Barkale, Sahil D. Vasishtha, Nilanjan Dey   +3 more
openaire   +2 more sources

Design of one-vector testable binary systems based on ternary logic

Proceedings of 26th IEEE International Symposium on Multiple-Valued Logic (ISMVL'96), 2002
A new concept, one-vector testability, is defined. Design method to achieve one-vector testability of binary systems based on ternary logic is proposed. Some techniques for designing testable binary systems based on ternary circuits are re-examined by using the proposed design method.
openaire   +1 more source

Performing Balanced Ternary Logic and Arithmetic Operations with Spiking Neural P Systems with Anti-Spikes

Advanced Materials Research, 2012
Spiking neural P systems are a class of distributed and parallel computing models inspired by P systems and spiking neural networks.Spiking neural P system with anti-spikes can encode the balanced ternary three digits in a natural way using three states called anti-spikes, no-input and spikes.
Xian Wu Peng, Xiao Ping Fan, Jian Xun Liu   +2 more
openaire   +1 more source

A general method for CMOS realization of any logic function in ternary computer system

2007 10th international conference on computer and information technology, 2007
This paper develops a general method for realization for any logic function using CMOS. By this new method, any ternary logic function can be realized by using only three unary and two binary functions. This method is more efficient than previously published CMOS realization.
openaire   +1 more source

Preeminent designing of complementary ternary TRANSFER and COMPLEMENT alongside excitation modulated molecular logic systems

Dalton Transactions
This article describes an optically adjustable, dual complementary ternary molecular TRANSFER & COMPLEMENT logic gate, besides an extremely rare design of excitation-modulated logic systems on a uni-molecular platform, triggered by chemical stimuli.
Monaj Karar, Rikitha S. Fernandes, Snehasish Saha, Nilanjan Dey   +3 more
openaire   +2 more sources

A power-aware design of a Spacer Detector for ternary logic asynchronous digital systems using conventional CMOS process technology

The 4th Joint International Conference on Information and Communication Technology, Electronic and Electrical Engineering (JICTEE), 2014
Recently, a C-ternary logic asynchronous digital system design was proposed. The advantage of this design was the use of conventional CMOS process technology, which reduced the process cost, instead of the multi-threshold one. However, the design had to use the element called “Spacer Detector”, or “SD”, to detect the half logic.
openaire   +1 more source

A Design of Low Voltage Spacer Detector Circuits for Asynchronous Ternary Logic System

TENCON 2023 - 2023 IEEE Region 10 Conference (TENCON), 2023
Pitchayapatchaya Srikram, Thanasin Bunnam   +1 more
openaire   +1 more source