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Two-Dimensions Vernier Time-to-Digital Converter
IEEE Journal of Solid-State Circuits, 2010A two-dimensions Vernier algorithm applied to a time to digital converter (TDC) is presented. The solution proposed minimizes the length of the delay lines used to perform the digital conversion leading to a better efficiency compared to traditional linear approaches.
VERCESI, LUCA +2 more
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Synchronization Algorithm in Time-to-Digital Converters Networks
2020 IEEE Nuclear Science Symposium and Medical Imaging Conference (NSS/MIC), 2020Nuclear physics experiments and medical imaging techniques like Positron Emission Tomography (PET) are moving through time- resolved experiments. Furthermore, the increasing complexity of the phenomena under observation makes mandatory to build a set-up by means of the interconnection of an instrumentation cluster.
F. Garzetti +5 more
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Background on Time-to-Digital Converters
2015For the first time, a third-order noise shaping concept has been successfully implemented in the design of time-to-digital converters (TDCs). Two 1-1-1 multistage noise shaping (MASH) \(\Delta\Sigma\) TDCs are presented in this chapter. Third-order time domain noise shaping has been adopted by the TDCs to achieve better than 6 ps resolution.
Ying Cao, Paul Leroux, Michiel Steyaert
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A wide range time-to-digital converter
Nuclear Instruments and Methods, 1975Abstract A 128-channel time-to-digital converter with a resolution from 0.5 μs up to 0.45 s per channel is described. The time base is taken from a crystal oscillator, which can be replaced by an RC-oscillator increasing the time width per channel up to 1000 s.
J. Bialkowski +2 more
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Time-to-Digital Converter Basics
2010On the basis of a generic mixed-signal system the scaling difficulties of analog and mixed-signal circuits based on a signal representation in the voltage domain are discussed for nanometer CMOS technologies. Therewith, the advantages of a signal representation in the time domain are emphasized.
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A Multihit Time-to-Digital Converter Architecture on FPGA
IEEE Transactions on Instrumentation and Measurement, 2009We present a multihit time-to-digital converter (TDC) architecture implemented in a field-programmable gate array (FPGA) with minimized timing overhead. The TDC circuit provides two-level fine-time interpolation. The fine interpolator is a matrix of Vernier delay cells interconnected in a topology to provide two propagation paths for the incoming data ...
A.M. Amiri, M. Boukadoum, A. Khouas
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A novel charge-pump based Time-to-Digital Converter
2009 IEEE Intrumentation and Measurement Technology Conference, 2009In this work, the design of a Time-to-Digital Converter (TDC) for measuring the time-of-flight (ToF) of a radio pulse is described. It consists on two blocks: a time-to-voltage transducer, whose scheme is that of a charge pump, designed using a 0.25 μm CMOS process, and an incremental first order sigma-delta (ΣΔ) converter. The two blocks are connected
NAPOLITANO, PASQUALE +2 more
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High-precision Time-to-Digital Converters in a FPGA device
2008 IEEE Nuclear Science Symposium Conference Record, 2008The construction and design process of a highresolution time-interval measuring system implemented in a SRAM-based FPGA device is discussed in this paper. The TDC can increase the precision on the measurement by interpolating time within the system clock cycle.
A. Aloisio +5 more
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Time-to-Digital converter with serial output interface
2008 International Conference on Signals and Electronic Systems, 2008Design of time-to-digital converter with a serial output interface for ADCs with asynchronous sigma-delta modulation is presented in details in the paper. The present paper is a continuation of the previous authors work. In particular, the concept and design of TDC control module is carefully explained.
Dariusz Koscielnik +2 more
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TMC-a CMOS time to digital converter VLSI
IEEE Transactions on Nuclear Science, 1989A novel time-to-digital converter CMOS VLSI chip has been developed. The main components of this TMC are memories and delay lines (buffers in series). Low-power and high-density characteristics have been attained by a submicron CMOS process and a novel circuit scheme utilizing variable-delay elements with a feedback circuit. Test results of a prototype
Y. Arai, T. Ohsugi
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