Results 41 to 50 of about 197,559 (299)
Research of a carry chain TDC and its tap method
Dianzi Jishu Yingyong, 2022 A time to digital converter(TDC) is implemented using carry chains in Xilinx Kinex-7 FPGA. FPGA-TDC is calibrated bin-by-bin through the code density calibration method.
Li Haitao +4 more
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Low-Resource Time-to-Digital Converters for Field Programmable Gate Arrays: A Review
SensorsA fundamental aspect in the evolution of Time-to-Digital Converters (TDCs) implemented within Field-Programmable Gate Arrays (FPGAs), given the increasing demand for detection channels, is the optimization of resource utilization.
Diego Real, David Calvo
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Employing FPGA DSP blocks for time-to-digital conversion [PDF]
Metrology and Measurement Systems, 2019 The paper presents a novel implementation of a time-to-digital converter (TDC) in field-programmable gate array (FPGA) devices. The design employs FPGA digital signal processing (DSP) blocks and gives more than two-fold improvement in mean resolution in ...
Paweł Kwiatkowski
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Remote Sensing, 2023 Lidar has emerged as an important technology for the high-precision three-dimensional remote sensing of the ocean. While oceanic lidar has been widely deployed on various platforms, its underwater deployment is relatively limited, despite its ...
Zaifa Lin +5 more
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Molecular Oncology, EarlyView.A‐to‐I editing of miRNAs, particularly miR‐200b‐3p, contributes to HGSOC progression by enhancing cancer cell proliferation, migration and 3D growth. The edited form is linked to poorer patient survival and the identification of novel molecular targets.
Magdalena Niemira +14 more
wiley +1 more source
Time-to-Digital Converter IP-Core for FPGA at State of the Art
IEEE Access, 2021 The Field Programmable Gate Array (FPGA) structure poses several constraints that make the implementation of complex asynchronous circuits such as Time–Mode (TM) circuits almost unfeasible.
Fabio Garzetti +3 more
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Compact algorithmic time‐to‐digital converter
Electronics Letters, 2015 Time‐to‐digital converters (TDCs) are an important circuit block in time‐of‐flight sensors, fluorescence lifetime sensors, and self‐calibrating digital circuits. Fine‐resolution TDCs are usually built with chains of delay elements, but this architecture requires large area, conversion time, and power consumption.
Shuo Li, Christopher D. Salthouse
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On time-interleaved analog-to-digital converters for digital transceivers [PDF]
2009 IEEE International Symposium on Circuits and Systems, 2009 This paper presents a transceiver model that comprises two time-interleaved analog-to-digital (A/D) converter systems to sample the inphase and quadrature signals in a digital receiver. Random data is used as the information signal and quadrature modulation is employed as the modulation scheme.
Soudan, Michael +2 more
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Screening for lung cancer: A systematic review of overdiagnosis and its implications
Molecular Oncology, EarlyView.Low‐dose computed tomography (CT) screening for lung cancer may increase overdiagnosis compared to no screening, though the risk is likely low versus chest X‐ray. Our review of 8 trials (84 660 participants) shows added costs. Further research with strict adherence to modern nodule management strategies may help determine the extent to which ...
Fiorella Karina Fernández‐Sáenz +12 more
wiley +1 more source
A Digital PLL with a Stochastic Time-to-Digital Converter [PDF]
2006 Symposium on VLSI Circuits, 2006. Digest of Technical Papers., 2006 A new dual-loop digital phase-locked loop (DPLL) architecture is presented. It employs a stochastic time-to-digital converter (STDC) and a high-frequency delta-sigma dithering to achieve wide PLL bandwidth and low jitter at the same time. The STDC exploits the stochastic properties of a set of latches to achieve high resolution.
V. Kratyuk +4 more
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