Research on the Coupling Effect of NBTI and TID for FDSOI pMOSFETs. [PDF]
Wei H +6 more
europepmc +1 more source
Novel approach to long-term monitoring of accelerator-based boron neutron capture therapy. [PDF]
Takada M +10 more
europepmc +1 more source
Synergistic Radiation Effects in PPD CMOS Image Sensors Induced by Neutron Displacement Damage and Gamma Ionization Damage. [PDF]
Wang ZJ +9 more
europepmc +1 more source
Metal-Halide Perovskite Submicrometer-Thick Films for Ultra-Stable Self-Powered Direct X-Ray Detectors. [PDF]
Girolami M +9 more
europepmc +1 more source
Systematic review of physical and dosimetric criteria for managing CIEDs in radiotherapy: A medical physicist's perspective. [PDF]
Malatesta T +15 more
europepmc +1 more source
The Route of Administration Determines the Efficacy of Zinc in Preventing Radiation-Induced Oral Mucositis: A Systematic Review and Meta-Analysis. [PDF]
Tsao CS, Wang KY, Liao CY.
europepmc +1 more source
Total Ionizing Dose (TID) Impact on Basic Amplifier Stages
<p>This paper discusses the impact of total ionizing dose (TID) on basic amplifier stages that are biased right above the device threshold voltages. Existing TID degradation-aware transistor models have been leveraged in circuit simulations.
Mustafa Berke Yelten, Sadik Ilik
exaly +4 more sources
Total Ionizing Dose (TID) Effects on Finger Transistors in a 65nm CMOS Process [PDF]
Although Total Ionizing Dose (TID) effects are generally unpronounced in deep-submicron-CMOS, we show the TID-induced leakage current @TID=500Krad is significant in NMOS-finger-transistors of GlobalFoundries 65nm CMOS.
Jize Jiang, Wei Shu
exaly +4 more sources
Ten-fold radiation levels are expected in the upgrade of the High-Luminosity Large Hadron Collider (HL-LHC) at CERN. Bulk silicon CMOS at 65 nm offers appreciable advantages among cost, performance, and resilience to high Total Ionizing Dose (TID).
Matthias Andrin Bucher +2 more
exaly +7 more sources
Summarization: High doses of ionizing radiation drastically impair the electrical performance of CMOS technology. Enclosed gate layout remains an effective means to reduce this impact.
Federico Faccio +2 more
exaly +4 more sources

