Results 181 to 190 of about 1,083 (193)

Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects

Nano Letters, 2020
Ali Saeidi, Teodor Rosca, Elvedin Memisevic   +2 more
exaly  

A Simulation Approach to Optimize the Electrical Parameters of a Vertical Tunnel FET

IEEE Transactions on Electron Devices, 2005
J Schulze, I Eisele
exaly  

Hetero-gate-Dielectric Symmetric U-shaped gate tunnel FET

Superlattices and Microstructures, 2017
Mohammad Bagher Tajally, Mohammad Azim Karami   +1 more
exaly  

Dielectric modulated overlapping gate-on-drain tunnel-FET as a label-free biosensor

Superlattices and Microstructures, 2015
Dawit Burusie Abdi, M Jagadesh Kumar
exaly  

Silicon tunnel FET with average subthreshold slope of 55 mV/dec at low drain currents

Solid-State Electronics, 2018
K Narimani, Qing-Tai Zhao, S Mantl
exaly  

Design and analysis of high k silicon nanotube tunnel FET device

IET Circuits, Devices and Systems, 2019
Avtar Singh, Saurabh Chaudhury, Chandan Kumar Pandey   +2 more
exaly  

${\rm Si}_{\rm x}{\rm Ge}_{1\hbox{-}{\rm x}}$ Epitaxial Tunnel Layer Structure for P-Channel Tunnel FET Improvement

IEEE Transactions on Electron Devices, 2013
Pei-Yu Wang, Bing-Yue Tsui
exaly  

A Physics-Based Model of Double-Gate Tunnel FET for Circuit Simulation

IETE Journal of Research, 2016
B Bindu
exaly  

Deep insight into linearity and NQS parameters of tunnel FET with emphasis on lateral straggle

Micro and Nano Letters, 2018
Sayani Ghosh, Kalyan Koley, Chandan K Sarkar   +2 more
exaly  

A Comparative Study of Junctionless Triple-Material Cylindrical Surrounding Gate Tunnel FET

Lecture Notes in Electrical Engineering, 2019
Sudhansu Mohan Biswal, Sanjit Kumar Swain, Umakanta Nanda   +2 more
exaly