Results 161 to 170 of about 1,083 (193)
Some of the next articles are maybe not open access.
Nanoscale Tunnel FETs for Internet-of-Things Applications
2018 IEEE SENSORS, 2018In this work, the RF performance comparison of lateral and vertical tunnel FETs is presented in the context of ultra low power (ULP) Internet-of-Things (IoT) sensor node circuit applications. It is demonstrated that at low drive currents $(\sim 1\mu \mathrm{A/\mu m})$ , LTFETs outperform VTFETs by an order higher cut-off frequency $(f_{\mathrm{T}})$
openaire +1 more source
Physics-based analytical model of nanowire tunnel-FETs
2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012In this work we propose a physics-based analytical model of nanowire tunnel FETs, which is meant to provide a fast tool for an optimized device design. The starting point of the model is the Landauer expression of the current for 1D physical systems, augmented with suitable expressions of the tunneling probability across the tunnel junctions and the ...
GNANI, ELENA +3 more
openaire +3 more sources
Applications of tunneling FET in memory devices
2010 10th IEEE International Conference on Solid-State and Integrated Circuit Technology, 2010Because of the special p-i-n structure of the tunneling FET (TFET), many different composite transistors can be formed with careful device design by combining TFET with MOSFET. In this paper, we propose the special applications of TFET as memory devices.
Song-Gan Zang +7 more
openaire +1 more source
2009
In Chap. 5 the integration of tunneling FETs in a low-power multi-gate technology is discussed as example for an alternative device concept and as outlook to analog design aspects beyond CMOS. Analog design considerations are derived from basic device performance, temperature and matching behavior.
openaire +1 more source
In Chap. 5 the integration of tunneling FETs in a low-power multi-gate technology is discussed as example for an alternative device concept and as outlook to analog design aspects beyond CMOS. Analog design considerations are derived from basic device performance, temperature and matching behavior.
openaire +1 more source
Characterization of Tunneling Resistance in Vertical Tunneling FETs
Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials, 2010A. Tura, J. C. S. Woo
openaire +1 more source
Tunnel FET Based SRAM Cells – A Comparative Review
Communications in Computer and Information Science, 2021Gadarapulla Rasheed +1 more
exaly
Tunnel FET Promise and Challenges
Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials, 2010T. -J. King Liu, S. H. Kim
openaire +1 more source