Results 161 to 170 of about 1,137 (197)
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2009
In Chap. 5 the integration of tunneling FETs in a low-power multi-gate technology is discussed as example for an alternative device concept and as outlook to analog design aspects beyond CMOS. Analog design considerations are derived from basic device performance, temperature and matching behavior.
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In Chap. 5 the integration of tunneling FETs in a low-power multi-gate technology is discussed as example for an alternative device concept and as outlook to analog design aspects beyond CMOS. Analog design considerations are derived from basic device performance, temperature and matching behavior.
openaire +1 more source
Nanoscale Tunnel FETs for Internet-of-Things Applications
2018 IEEE SENSORS, 2018In this work, the RF performance comparison of lateral and vertical tunnel FETs is presented in the context of ultra low power (ULP) Internet-of-Things (IoT) sensor node circuit applications. It is demonstrated that at low drive currents $(\sim 1\mu \mathrm{A/\mu m})$ , LTFETs outperform VTFETs by an order higher cut-off frequency $(f_{\mathrm{T}})$
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High-K Biomolecule Sensor Based on L-Shaped Tunnel FET
Lecture Notes in Electrical Engineering, 2021Abhijit Mallik +2 more
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Characterization of Tunneling Resistance in Vertical Tunneling FETs
Extended Abstracts of the 2010 International Conference on Solid State Devices and Materials, 2010A. Tura, J. C. S. Woo
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Tunnel FET Based SRAM Cells – A Comparative Review
Communications in Computer and Information Science, 2021Sridevi Sriadibhatla +1 more
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Optimization of Negative-Capacitance Vertical-Tunnel FET (NCVT-FET)
IEEE Transactions on Electron Devices, 2020Vita Pi-Ho Hu +2 more
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