Results 151 to 160 of about 1,137 (197)
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Noise behavior of ferro electric tunnel FET
Microelectronics Journal, 2020Abstract In this paper the noise behavior of ferroelectric TFET is explored for the first time. The effect of ferro-thickness, gate length, buffer type, and buffer thickness on current noise power spectral Density (SID) and voltage noise power spectral Density (SVG) along with electrical parameters such as memory window, subthreshold swing along with
Basab Das, Brinda Bhowmick
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2016
As discussed in the previous sections, the SS of the MOSFET governed by the Boltzmann tyranny (herein, the theoretical limit of SS is ~60 mV/decade at 300 K) is a main bottleneck in scaling down the power supply voltage (V DD ) as well as extensively reducing the power consumption in integrated circuits (ICs).
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As discussed in the previous sections, the SS of the MOSFET governed by the Boltzmann tyranny (herein, the theoretical limit of SS is ~60 mV/decade at 300 K) is a main bottleneck in scaling down the power supply voltage (V DD ) as well as extensively reducing the power consumption in integrated circuits (ICs).
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A nanoscale vertical-tunneling FET
1995 53rd Annual Device Research Conference Digest, 2002Simulates silicon-based FETs having a radically new architecture, one which could eventually permit scaling of overall device dimensions to 500A or less while simultaneously eliminating the large-area contacts and isolation required in conventional MOSFETs.
J.R. Tucker, C. Wang, T.-C. Shen
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The Hysteretic Ferroelectric Tunnel FET
IEEE Transactions on Electron Devices, 2010We present the fabrication and the electrical characterization of ferroelectric tunnel FETs (Fe-TFETs). This novel family of hysteretic switches combines the low subthreshold power of band-to-band tunneling devices with the retention characteristics of Fe gate stacks, offering some interesting features for future one-transistor (1T) memory cells.
Ionescu, Adrian M. +5 more
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Understanding of BTI for tunnel FETs
2015 IEEE International Electron Devices Meeting (IEDM), 2015We systematically investigated the NBTI degradation of Si-channel p-type tunnel FETs (pTFETs). The NBTI degradation mechanism of pTFETs is almost the same as that of pFETs. It was clarified that the NBTI degradation of pTFETs is only caused by the trap charge and the interface state degradation located in the tunneling region near the n+ source/gate ...
W. Mizubayashi +13 more
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Complementary III–V heterostructure tunnel FETs
2016 46th European Solid-State Device Research Conference (ESSDERC), 2016In the present work we will show our complementary TFET technology, which allows for the co-planar integration of InAs/Si p-TFETs and InAs/GaSb n-TFETs. We demonstrate both types of devices, show the results of the electrical characterization at room temperature and down to 125K. The p-TFETs exhibit excellent performance with I on of a couple of µA/µm
Kirsten E. Moselund +5 more
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Tunneling FET Fabrication and Characterization
2016Since the early demonstration of the conventional p + −i − n + Tunneling FETs (TFETs), various tunneling junction designs as well as the introduction of new material systems enabled the performance of TFETs to improve by orders of magnitude. Different properties and considerations of the material systems require well designed processes and novel ...
Tao Yu +2 more
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Steep slope transistors: Tunnel FETs and beyond
2016 46th European Solid-State Device Research Conference (ESSDERC), 2016Low voltage transistors are being developed to achieve steep, less than 60 mV/decade, subthreshold swings at room temperature. This paper outlines progress, technical challenges, and applications for these devices.
Alan C. Seabaugh +9 more
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Analog Circuit Design Using Tunnel-FETs
IEEE Transactions on Circuits and Systems I: Regular Papers, 2015Tunnel-FET (TFET) is a major candidate for beyond-CMOS technologies. In this paper, the properties of the TFETs that affect analog circuit design are studied. To demonstrate how TFETs can enhance the performance or change the topology of the analog circuits, several building blocks such as operational transconductance amplifiers (OTAs), current mirrors,
Behnam Sedighi +4 more
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Superlattices and Microstructures, 2016
Abstract In this paper, we propose a novel tunnel field-effect transistor (TFET) based on charge plasma (CP) and negative capacitance (NC) for enhanced ON-current and steep subthreshold swing (SS). It is shown that the replacement of standard insulator for gate stack with ferroelectric (Fe) insulator yields NC and high electric field at the tunneling
Avinash Lahgere +2 more
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Abstract In this paper, we propose a novel tunnel field-effect transistor (TFET) based on charge plasma (CP) and negative capacitance (NC) for enhanced ON-current and steep subthreshold swing (SS). It is shown that the replacement of standard insulator for gate stack with ferroelectric (Fe) insulator yields NC and high electric field at the tunneling
Avinash Lahgere +2 more
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