Results 141 to 150 of about 1,137 (197)

A Tunnel Dielectric-Based Tunnel FET

IEEE Electron Device Letters, 2015
In this letter, for the first time, we proposed and demonstrated a novel tunnel dielectric-based tunnel FET (TD-TFET). Instead of using semiconductor band-to-band tunneling currents to form drive currents as in normal TFET, tunneling currents through ultrathin dielectric form the drive currents in the TD-TFET. The fabricated devices have achieved 55-mV/
Zhijiong Luo, Hefei Wang, Ning An, Zhengyong Zhu   +3 more
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SiGe Tunnel FETs

ECS Meeting Abstracts, 2008
Abstract not Available.
Ignaz Eisele, Martin Schlosser
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Schottky Tunneling Effects in a Tunnel FET

IEEE Transactions on Electron Devices, 2017
Tunnel FETs (TFETs) have attracted a great deal of attention due to their steep subthreshold swing (SS) of less than 60 mV/dec, which overcomes the theoretical constraint imposed by the thermal limit in a conventional inversion-mode (IM) FET. Based on its advantages as a short-channel device with low stand-by power consumption, TFETs shows promise to ...
Jae Hur, Woo Jin Jeong, Mincheol Shin, Yang-Kyu Choi   +3 more
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Tunnel FET technology: A reliability perspective

Microelectronics Reliability, 2014
Abstract Tunneling-field-effect-transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage ( V DD ) scaling in ultra-low power, energy efficient computing, due to its sub-60 mV/decade sub-threshold slope (SS).
Suman Datta, Huichu Liu, Vijaykrishnan Narayanan   +2 more
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Atomistic Simulations of Tunneling FETs

2016
© Springer International Publishing Switzerland 2016.With continuous scaling of semiconductor devices, the number of atoms in transistors becomes countable. Various effects related to the device atomic structure, such as random dopants, edge roughness, and channel-oxide interface, have great impact on device performance.
Liu, Fei, Shi, Qing, Wang, Jian, Guo, Hong   +3 more
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A Novel Tunnel Oxide Based Tunnel FET

ECS Transactions, 2011
In this work, we propose a novel tunnel oxide based Tunnel FET. This novel Tunnel FET can achieve high drive currents, low SS, low off currents and many other superb device characteristics. From device simulation, this novel device can obtain drive currents 100x higher than that of a conventional Tunnel FET. This novel device also can realize SS as low
Hefei Wang, Zhijiong Luo, Haizhou Yin, Huilong Zhu, Jia Liu, Zhengyong Zhu   +5 more
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Tunnel FET based refresh-free-DRAM

Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017
A refresh free and scalable ultimate DRAM (uDRAM) bitcell and architecture is proposed for embedded application. uDRAM 1T1C bitcell is designed using access Tunnel FETs. Proposed design is able to store the data statically during retention eliminating the need for refresh.
Gupta, Navneet, Makosiej, Adam, Vladimirescu, Andrei, Amara, Amara, Anghel, Costin   +4 more
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Simulation of the Esaki-tunneling FET

Solid-State Electronics, 2003
Abstract As the dimension of the metal oxide semiconductor field effect transistor (MOSFET) keeping scaling, the short channel effects are becoming serious problems. Recently a MOS-based vertical tunneling transistor in silicon was proposed as a possible successor of the MOSFET.
Peng-Fei Wang, Thomas Nirschl, Doris Schmitt-Landsiedel, Walter Hansch   +3 more
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Resonant interband tunneling FET

IEEE Electron Device Letters, 1995
A lateral three-terminal Resonant Interband Tunneling Field Effect Transistor (RITFET) has been fabricated. It consists of a resonant interband tunnel diode (RITD) built using the GaSb-AlSb-InAs material system and a pseudomorphic InGaAs channel FET in which the current is controlled by a Schottky gate.
S. Tehrani, J. Shen, H. Goronkin, G. Kramer, R. Tsui, T.X. Zhu   +5 more
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Innovative tunnel FET architectures

2018 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EUROSOI-ULIS), 2018
We propose three innovative SOI Tunnel FET architectures. They are evaluated and compared with a standard TFET structure using Sentaurus TCAD. The extension of the source (anode) at the bottom of the body generates vertical band-to-band tunneling with a very steep slope and higher ION than lateral tunneling, but only for gate lengths longer than 100 nm.
Llorente, Carlos Diaz, Martinie, Sébastien, Cristoloveanu, Sorin, Colinge, Jean-Pierre, Le Royer, Cyrille, Ghibaudo, Gérard, Wan, Jing, Vinet, Maud   +7 more
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