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Schottky Tunneling Effects in a Tunnel FET
IEEE Transactions on Electron Devices, 2017Tunnel FETs (TFETs) have attracted a great deal of attention due to their steep subthreshold swing (SS) of less than 60 mV/dec, which overcomes the theoretical constraint imposed by the thermal limit in a conventional inversion-mode (IM) FET. Based on its advantages as a short-channel device with low stand-by power consumption, TFETs shows promise to ...
Jae Hur +3 more
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Tunnel FET technology: A reliability perspective
Microelectronics Reliability, 2014Abstract Tunneling-field-effect-transistor (TFET) has emerged as an alternative for conventional CMOS by enabling the supply voltage ( V DD ) scaling in ultra-low power, energy efficient computing, due to its sub-60 mV/decade sub-threshold slope (SS).
Suman Datta +2 more
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ECS Meeting Abstracts, 2008
Abstract not Available.
Ignaz Eisele, Martin Schlosser
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Abstract not Available.
Ignaz Eisele, Martin Schlosser
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2017 International Conference on Nextgen Electronic Technologies: Silicon to Software (ICNETS2), 2017
The impact of technology scaling vividly increases the susceptibility of semiconductor devices to radiation. Single Event Transient (SET) in a device is a process in which the generation of charge takes place when a single particle passes through a sensitive node in the device. This paper deals with the performance analysis of three different tunneling
R. Gowri Manohari +2 more
exaly +2 more sources
The impact of technology scaling vividly increases the susceptibility of semiconductor devices to radiation. Single Event Transient (SET) in a device is a process in which the generation of charge takes place when a single particle passes through a sensitive node in the device. This paper deals with the performance analysis of three different tunneling
R. Gowri Manohari +2 more
exaly +2 more sources
Compact modeling of homojunction tunnel FETs
2014 Proceedings of the 21st International Conference Mixed Design of Integrated Circuits and Systems (MIXDES), 2014Aggressive scaling of the supply voltage reduces the energy needed for switching of standard CMOS devices. However, advanced CMOS technologies are facing two main problems that consequently lead to higher power consumption: the complexity of a further supply voltage reduction, and the rising leakage currents that directly affect the switching ratio ...
Arnab Biswas +6 more
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Tunnel FET based refresh-free-DRAM
Design, Automation & Test in Europe Conference & Exhibition (DATE), 2017, 2017A refresh free and scalable ultimate DRAM (uDRAM) bitcell and architecture is proposed for embedded application. uDRAM 1T1C bitcell is designed using access Tunnel FETs. Proposed design is able to store the data statically during retention eliminating the need for refresh.
Gupta, Navneet +4 more
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Resonant interband tunneling FET
IEEE Electron Device Letters, 1995A lateral three-terminal Resonant Interband Tunneling Field Effect Transistor (RITFET) has been fabricated. It consists of a resonant interband tunnel diode (RITD) built using the GaSb-AlSb-InAs material system and a pseudomorphic InGaAs channel FET in which the current is controlled by a Schottky gate.
S. Tehrani +5 more
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Atomistic Simulations of Tunneling FETs
2016© Springer International Publishing Switzerland 2016.With continuous scaling of semiconductor devices, the number of atoms in transistors becomes countable. Various effects related to the device atomic structure, such as random dopants, edge roughness, and channel-oxide interface, have great impact on device performance.
Liu, Fei +3 more
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Simulation of the Esaki-tunneling FET
Solid-State Electronics, 2003Abstract As the dimension of the metal oxide semiconductor field effect transistor (MOSFET) keeping scaling, the short channel effects are becoming serious problems. Recently a MOS-based vertical tunneling transistor in silicon was proposed as a possible successor of the MOSFET.
Peng-Fei Wang +3 more
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Noise behavior of ferro electric tunnel FET
Microelectronics Journal, 2020Abstract In this paper the noise behavior of ferroelectric TFET is explored for the first time. The effect of ferro-thickness, gate length, buffer type, and buffer thickness on current noise power spectral Density (SID) and voltage noise power spectral Density (SVG) along with electrical parameters such as memory window, subthreshold swing along with
Basab Das, Brinda Bhowmick
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