Results 201 to 210 of about 606,110 (277)
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IEEE Transactions on Electron Devices, 2020
This article investigates the performance of a vertically grown GaSb/Si tunnel field effect transistor (V-TFET) with a source pocket to enhance the performance of the device.
M. Tripathy +6 more
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This article investigates the performance of a vertically grown GaSb/Si tunnel field effect transistor (V-TFET) with a source pocket to enhance the performance of the device.
M. Tripathy +6 more
semanticscholar +1 more source
IEEE transactions on nanotechnology, 2021
The objective of this paper is to exemplify the significant improvements achieved in speed and power-consumption by utilizing negative-capacitance Tunnel FETs in sub-0.4 VDD digital logic applications.
S. Guha, Prithviraj Pachal
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The objective of this paper is to exemplify the significant improvements achieved in speed and power-consumption by utilizing negative-capacitance Tunnel FETs in sub-0.4 VDD digital logic applications.
S. Guha, Prithviraj Pachal
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Atomistic Simulations of Tunneling FETs
2016© Springer International Publishing Switzerland 2016.With continuous scaling of semiconductor devices, the number of atoms in transistors becomes countable. Various effects related to the device atomic structure, such as random dopants, edge roughness, and channel-oxide interface, have great impact on device performance.
Liu, Fei +3 more
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IEEE Sensors Journal, 2021
In this work, a Diagonal Tunneling Dielectrically Modulated Tunnel Field Effect Transistor (DT-DMTFET) architecture is proposed for label-free bio-sensing application.
S. Mukhopadhyay +4 more
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In this work, a Diagonal Tunneling Dielectrically Modulated Tunnel Field Effect Transistor (DT-DMTFET) architecture is proposed for label-free bio-sensing application.
S. Mukhopadhyay +4 more
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A nanoscale vertical-tunneling FET
1995 53rd Annual Device Research Conference Digest, 2002Simulates silicon-based FETs having a radically new architecture, one which could eventually permit scaling of overall device dimensions to 500A or less while simultaneously eliminating the large-area contacts and isolation required in conventional MOSFETs.
J.R. Tucker, C. Wang, T.-C. Shen
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The Hysteretic Ferroelectric Tunnel FET
IEEE Transactions on Electron Devices, 2010We present the fabrication and the electrical characterization of ferroelectric tunnel FETs (Fe-TFETs). This novel family of hysteretic switches combines the low subthreshold power of band-to-band tunneling devices with the retention characteristics of Fe gate stacks, offering some interesting features for future one-transistor (1T) memory cells.
Adrian M. Ionescu +5 more
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Tunnel FETs with tunneling normal to the gate
2013 Third Berkeley Symposium on Energy Efficient Electronic Systems (E3S), 2013Summary form only given. In this talk, I will review some of the recent development of tunnel field effect transistors (TFETs) at Notre Dame [1-8]. Tunnel FETs are promising replacements of Si-MOSFETs beyond 2020 due to their promise to achieve Ion/Ioff > 103 with Ion > 100 uA/um at low supply voltages (up to 0.5 V).
Huili Grace Xing +8 more
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IEEE Transactions on Electron Devices, 2020
In this article, for the first time, the performance of a double-hetero-gated-dielectric-modulated tunnel FET (DHGDM-TFET) biosensor device, having channel length ( ${L}_{\text{ch}}$ ) of 50 nm, is thoroughly investigated in terms of threshold voltage- (
Sampriti Ghosh +2 more
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In this article, for the first time, the performance of a double-hetero-gated-dielectric-modulated tunnel FET (DHGDM-TFET) biosensor device, having channel length ( ${L}_{\text{ch}}$ ) of 50 nm, is thoroughly investigated in terms of threshold voltage- (
Sampriti Ghosh +2 more
semanticscholar +1 more source
2016
As discussed in the previous sections, the SS of the MOSFET governed by the Boltzmann tyranny (herein, the theoretical limit of SS is ~60 mV/decade at 300 K) is a main bottleneck in scaling down the power supply voltage (V DD ) as well as extensively reducing the power consumption in integrated circuits (ICs).
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As discussed in the previous sections, the SS of the MOSFET governed by the Boltzmann tyranny (herein, the theoretical limit of SS is ~60 mV/decade at 300 K) is a main bottleneck in scaling down the power supply voltage (V DD ) as well as extensively reducing the power consumption in integrated circuits (ICs).
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Physics-based analytical model of nanowire tunnel-FETs
2012 IEEE 11th International Conference on Solid-State and Integrated Circuit Technology, 2012In this work we propose a physics-based analytical model of nanowire tunnel FETs, which is meant to provide a fast tool for an optimized device design. The starting point of the model is the Landauer expression of the current for 1D physical systems, augmented with suitable expressions of the tunneling probability across the tunnel junctions and the ...
GNANI, ELENA +3 more
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