Results 181 to 190 of about 8,846,054 (209)

A Process-Aware Compact Model for GIDL-Assisted Erase Optimization of 3-D V-NAND Flash Memory

IEEE Transactions on Electron Devices, 2023
This article presents the accurate compact modeling methodology to optimize the gate-induced drain leakage (GIDL)-assisted erase operation for vertical stack-up, multiple stack, and ${Z}$ -directional shrink of the 3-D vertically integrated NAND (V-NAND)
Yohan Kim, Soyoung Kim
openaire   +2 more sources

11.4 A 512Gb 3b/cell 64-stacked WL 3D V-NAND flash memory

2017 IEEE International Solid-State Circuits Conference (ISSCC), 2017
The advent of emerging technologies such as cloud computing, big data, the internet of things and mobile computing is producing a tremendous amount of data. In the era of big data, storage devices with versatile characteristics are required for ultra-fast processing, higher capacity storage, lower cost, and lower power operation. SSDs employing 3D NAND
Chulbum Kim, Ji-Ho Cho, Woopyo Jeong, Il-han Park, Hyun-Wook Park, Doo-Hyun Kim, Daewoon Kang, Sunghoon Lee, Ji-Sang Lee, Wontae Kim, Jiyoon Park, Yang-lo Ahn, Jiyoung Lee, Jong-hoon Lee, Seungbum Kim, Hyun-Jun Yoon, Jaedoeg Yu, Nayoung Choi, Yelim Kwon, Nahyun Kim, Hwajun Jang, Jonghoon Park, Seunghwan Song, Yongha Park, Jinbae Bang, Sangki Hong, Byunghoon Jeong, Hyun-Jin Kim, Chunan Lee, Young-Sun Min, Inryul Lee, In-Mo Kim, Sung-Hoon Kim, Dongkyu Yoon, Ki-Sung Kim, Youngdon Choi, Moosung Kim, Hyunggon Kim, Pansuk Kwak, Jeong-Don Ihm, Dae-Seok Byeon, Jin-yub Lee, Ki-Tae Park, Kye-hyun Kyung   +43 more
semanticscholar   +4 more sources

Demonstration of Multi-layered Macaroni Filler for Back-Biasing-Assisted Erasing Configuration in 3D V-NAND

JOURNAL OF SEMICONDUCTOR TECHNOLOGY AND SCIENCE, 2021
—Controlling the erase speed of a NAND flash is one of the challenges in memory technology. As the planar NAND flash has evolved to the vertically integrated gate-all-around (GAA), the number of stacks of word-lines (WL) was increased for better packing ...
Dae-Han Jung, Khwang-Sun Lee, Jun-Young Park   +2 more
openaire   +2 more sources

Impact of High-k Bandgap Engineering on V-NAND Cell Performance

IEEE Electron Device Letters
We propose an optimized high-k bandgap engineering structure to meet the demands of high-capacity vertical NAND (V-NAND). Simulation results show that the HfO2/Si3N4/Oxide (H/N/O) structure exhibits superior program/erase (P/E) characteristics compared ...
Myeongsang Yun, Gyuhyeon Lee, Gunwook Yoon, Seungjae Baik, Myounggon Kang   +4 more
openaire   +2 more sources

Proposal of Tilt-Axis Adjustment in V-NAND Plan-View without Si Substrate Using Automated Metrology of Transmission Electron Microscope

International Symposium for Testing and Failure Analysis, 2023
Abstract In this paper, we propose a method to get more accurate metrology data using the tilt-axis on a transmission electron microscope (TEM) to compensate for microscopic tilt-axis changes that occur during focused ion beam (FIB) sample preparation processing.
Dong-yeob Kim, Su-yeon Kim, Woo-jun Kwon, Min-kook Kim, Christopher H. Kang   +4 more
openaire   +2 more sources

Self-Heating Effects in 3-D Vertical-NAND (V-NAND) Flash Memory

IEEE Transactions on Electron Devices, 2020
Self-heating effects (SHEs) were investigated through simulations for 3-D V- NAND flash memory. The SHEs are varied by adjusting the thickness of the poly-crystalline channel, the number of stacked cells along with a bitline, and the configuration of the multilevel cell.
Gyeong-Jun Yun, Dae-Hwan Yun, Jun-Young Park, Seong-Yeon Kim, Yang-Kyu Choi   +4 more
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Highly Scalable Vertical Bypass RRAM (VB-RRAM) for 3D V -NAND Memory

2024 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)
We firstly demonstrate highly scalable interface type RRAM based 3D V-NAND memory with WOx resistivity switching (RS) layer and IGZO selector transistor (Tr).
Geonhui Han, Youngdong Kim, Jaeseon Kim, Dongmin Kim, Yoori Seo, Chuljun Lee, Jinmyung Choi, Jinwoo Lee, Dongho Ahn, Sechung Oh, Donghwa Lee, Hyunsang Hwang   +11 more
openaire   +2 more sources

Strategic Material Design for Highly Reliable QLC 3D V-NAND Using Bypass Resistive Random Access Memory

ACS Applied Materials & Interfaces
To overcome the limitation of conventional flash memory, electrochemical random-access memory (ECRAM)-based bypass memory (bypass RRAM) has been proposed as a potential candidate for V-NAND memory application. While bypass RRAM demonstrates excellent memory characteristics through ion hopping conduction, the key parameters governing multilevel cell ...
Geonhui Han, Jongseon Seo, Junghoon Park, Minji Hong, Juhyung Kim, Kilho Lee, Wanki Kim, Daewon Ha, Hyunsang Hwang   +8 more
openaire   +3 more sources

Effect of Device Scaling on Lateral Migration Mechanism of Electrons in V-NAND

2019 Silicon Nanoelectronics Workshop (SNW), 2019
In this paper, we analyzed lateral migration (LM) mechanism of V-NAND occurring during retention operation depending on scaling of geometric parameters using TCAD simulation. Modeling for LM was performed and the behavior of time-constant (τ) parameter used for modeling was analyzed.
Changbeom Woo, Shinkeun Kim, Jaeyeol Park, Hyungcheol Shin   +3 more
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Spatial Charge Trap Engineering with Boron Nitride Barrier for 3D V-NAND Flash Memory

2024 IEEE International Electron Devices Meeting (IEDM)
Spatial charge trap engineering using amorphous boron nitride (BN) energy barrier for 3D V-NAND flash memory device is presented. A 1 nm thick BN layer is inserted within a silicon nitride (SiN) charge trap layer (CTL) using an In-situ ALD process.
Dae Hyun Kang, Jae Joong Jeong, Young Keun Park, Dong Hun Sin, Han Mei Choi, Byung Jin Cho   +5 more
openaire   +2 more sources