Results 11 to 20 of about 36,083 (304)
VENICE: A Compact Vector Processor for FPGA Applications [PDF]
2012 IEEE 20th International Symposium on Field-Programmable Custom Computing Machines, 2011 This article consists of a collection of slides from the author's conference presentation on VENICE (Vector Extensions to NIOS Implemented Compactly and Elegantly), a SVP (soft vector processor) intended to accelerate computationally intensive applications implemented on an FPGA.
Aaron Severance, Guy Lemieux
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Accelerator compiler for the VENICE vector processor [PDF]
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays, 2012 This paper describes the compiler design for VENICE, a new soft vector processor (SVP). The compiler is a new back-end target for Microsoft Accelerator, a high-level data parallel library for C++ and C#. This allows us to automatically compile high-level programs into VENICE assembly code, thus avoiding the process of writing assembly code used by ...
Zhiduo Liu +3 more
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QR Factorization on a Long-Vector Processor
We build two high-performance implementations of the QR factorization optimized for the long vector units in the accelerator developed as part of the European Processor Initiative. Both realizations, based on the Householder and Gram-Schmidt (GS) methods respectively, are optimized via linear algebra kernels that can be reused for other applications ...
Andrés E. Tomás +3 more
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Design of Processor Array Based on an Optimized Multiprojection Approach [PDF]
Advances in Electrical and Computer Engineering, 2012 Parallelization methodologies allow to automate the process of designing optimal processor arrays based on mathematical representations of the algorithm to be implemented.
CAMPOS, J.-M, CUMPLIDO, R.
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An Energy-Efficient ECG Processor Based on HDWT and a Hybrid Classifier for Arrhythmia Detection
Applied Sciences, 2023 Cardiac arrhythmia (CA) is a severe cardiac disorder that results in a significant number of fatalities worldwide each year. Conventional electrocardiography (ECG) devices are often unable to detect arrhythmia symptoms during patients’ hospital visits ...
Jiawen Deng +6 more
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Polynomial multiplication on embedded vector architectures
Transactions on Cryptographic Hardware and Embedded Systems, 2021 High-degree, low-precision polynomial arithmetic is a fundamental computational primitive underlying structured lattice based cryptography. Its algorithmic properties and suitability for implementation on different compute platforms is an active area of ...
Hanno Becker +4 more
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Research on LLM Vector Dot Product Acceleration Based on RISC-V Matrix Instruction Set Extension [PDF]
Jisuanji kexueConsidering the high-performance and low-power requirements of edge AI,this paper designs a specialized instruction set processor for edge AI based on the RISC-V instruction set architecture,addressing practical issues in digital signal processing for ...
CHEN Xuhao, HU Sipeng, LIU Hongchao, LIU Boran, TANG Dan, ZHAO Di
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Realization and Performance Analysis of Matrix Multiplication on HXDSP Platform [PDF]
Jisuanji gongcheng, 2019 Matrix operations on vector processors face the problems of low utilization of hardware resources and low data processing capacity.Therefore,based on HX Digital Signal Processor(HXDSP) platform,combined with Discrete Cosine Transform(DCT) algorithm in ...
LIU Yufu,LANG Wenhui,JIA Guangshuai
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A Language for Array and Vector Processors [PDF]
ACM Transactions on Programming Languages and Systems, 1979 The scientific community has consistently demanded from computing machines an increase in the number of instructions executed per second. The latest increase has been achieved by duplication of arithmetic units for an array processor and the pipelining of functional units for vector processors.
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A C++-embedded Domain-Specific Language for programming the MORA soft processor array [PDF]
, 2010 MORA is a novel platform for high-level FPGA programming of streaming vector and matrix operations, aimed at multimedia applications. It consists of soft array of pipelined low-complexity SIMD processors-in-memory (PIM).
Purohit, S. +7 more
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