Results 21 to 30 of about 36,083 (304)
Vitruvius+: An area-efficient RISC-V decoupled vector coprocessor for high performance computing applications [PDF]
, 2023 The maturity level of RISC-V and the availability of domain-specific instruction set extensions, like vector processing, make RISC-V a good candidate for supporting the integration of specialized hardware in processor cores for the High Performance ...
Marimon Illana, Joan +23 more
core +1 more source
Advances in Electrical and Computer Engineering, 2019 This paper presents the authors' research in the field of specialized optimizing assembly language compilers for embedded real-time soft-core processor systems on FPGAs.
KIRCHHOFF, M., WAGNER, L., FENGLER, W.
doaj +1 more source
Reusable Verification Environment for a RISC-V Vector Accelerator [PDF]
, 2023 This paper presents a reusable verification environment developed for the verification of an academic RISC-V based vector accelerator that operates with long vectors.
Díaz, Ivan +9 more
core +1 more source
Power Electronics and Drives, 2018 The purpose of the article was to present the idea of space vector pulse width modulation (SVPWM) and implementation in Nios II softcore processor.
Chojowski Maciej
doaj +1 more source
Photonic Integrated Reconfigurable Linear Processors as Neural Network Accelerators
Applied Sciences, 2021 Reconfigurable linear optical processors can be used to perform linear transformations and are instrumental in effectively computing matrix–vector multiplications required in each neural network layer.
Lorenzo De Marinis +5 more
doaj +1 more source
Dual Vector Load for Improved Pipelining in Vector Processors
2023 IEEE Symposium in Low-Power and High-Speed Chips (COOL CHIPS), 2023 Vector processors execute instructions that manipulate vectors of data items using time-division multiplexing (TDM). Chaining, the pipelined execution of vector instruction, ensures high performance and utilization. When two vectors are loaded sequentially to be the input of a follow-up compute instruction, which is often the case in vector ...
Viktor Razilov +3 more
openaire +2 more sources
A Geometric Algebra Co-Processor for Color Edge Detection
, 2015 This paper describes advancement in color edge detection, using a dedicated Geometric Algebra (GA) co-processor implemented on an Application Specific Integrated Circuit (ASIC).
Wilcock, Reuben +5 more
core +1 more source
Energies, 2020 This paper investigates the implementation of a wide-adjustable sensorless interior permanent magnet synchronous motor drive based on current deviation detection under space-vector modulation.
Muhammad Syahril Mubarok +3 more
doaj +1 more source
Channel Estimation for Advanced 5G/6G Use Cases on a Vector Digital Signal Processor
IEEE Open Journal of Circuits and Systems, 2021 As we target implementations of very high-end () specifications and look towards the future, it becomes apparent that the stringent execution deadlines in physical layer (PHY) procedures are hard to satisfy using traditional algorithms optimised for high
Stefan A. Damjancevic +4 more
doaj +1 more source
Speculative Vectorization for Superscalar Processors
, 2023 Traditional vector architectures have been shown to be very effective in executing regular codes in which the compiler can detect data-level parallelism, i.e. repeating the same computation over different elements in the same code-level data structure.<br/><br/>A skilled programmer can easily create efficient vector code from regular ...
openaire +5 more sources