Results 41 to 50 of about 36,083 (304)

A compiler extension for parallelizing arrays automatically on the cell heterogeneous processor [PDF]

, 2012
This paper describes the approaches taken to extend an array programming language compiler using a Virtual SIMD Machine (VSM) model for parallelizing array operations on Cell Broadband Engine heterogeneous machine.
Cockshott, W., Gdura, Y.
core  

Superscalar RISC-V Processor with SIMD Vector Extension [PDF]

, 2020
With the increasing number of digital products in the market, the need for robust and highly configurable processors rises. The demand is convened by the stable and extensible open-sourced RISC-V instruction set architecture.
He, Jiongrui
core  

Efficient binary phase quantizer based on phase sensitive four wave mixing [PDF]

, 2014
We experimentally demonstrate an efficient binary phase quantizer operating at low pump powers. Phase-sensitive operation is obtained by polarization mixing the phase-locked signal/idler pair in a degenerate dual-pump vector parametric ...
Horak, P., P. Horak, Hesketh, G., D. J. Richardson, Parmigiani, F., Slavík, R., Petropoulos, P., F. Parmigiani, Richardson, D.J., P. Petropoulos, G. Hesketh, R. Slavik   +11 more
core   +1 more source

Structural insights into an engineered feruloyl esterase with improved MHET degrading properties

FEBS Letters, EarlyView.
A feruloyl esterase was engineered to mimic key features of MHETase, enhancing the degradation of PET oligomers. Structural and computational analysis reveal how a point mutation stabilizes the active site and reshapes the binding cleft, expading substrate scope.
Panagiota Karampa, Konstantinos Makryniotis, Theofani‐Iosifina Sousani, Evangelos Topakas, Vangelis Daskalakis, Maria Dimarogona   +5 more
wiley   +1 more source

Auto-vectorization: recent development and prospect

Tongxin xuebao, 2022
The technology of SIMD is developing rapidly, and quite a few auto-vectorization methods have been proposed.Auto-vectorization can automatically translate scalar programs into vector programs based on SIMD extension, decrease workload of the programmers ...
Jingge FENG, Yeping HE, Qiuming TAO
doaj   +2 more sources

PF-GEMV: Utilization maximizing architecture in fast matrix-vector multiplication for GPT-2 inference

ETRI Journal
Owing to the widespread advancement of transformer-based artificial neural networks, artificial intelligence (AI) processors are now required to perform matrix-vector multiplication in addition to the conventional matrix-matrix multiplication.
Hyeji Kim, Yeongmin Lee, Chun-Gi Lyuh
doaj   +1 more source

Task Mapping and Scheduling on RISC-V MIMD Processor With Vector Accelerator Using Model-Based Parallelization

IEEE Access
In this paper, we propose a model-based workflow to generate parallel code on a multiple instruction stream, multiple data stream (MIMD) processor with vector accelerator (MIMDV) from a Simulink model. Solving data- and task-parallelism is crucial during
Shanwen Wu, Satoshi Kumano, Kei Marume, Masato Edahiro   +3 more
doaj   +1 more source

On the hardware reduction of z-datapath of vectoring CORDIC

, 2007
In this article we present a novel design of a hardware optimal vectoring CORDIC processor. We present a mathematical theory to show that using bipolar binary notation it is possible to eliminate all the arithmetic computations required along the z ...
J. Mathew, Nunez-Yanez, Jose, J.L. Nunez-Yanez, K. Maharatna, Pradhan, Dhiraj, Maharatna, Koushik, Stapenhurst, Robert, Matthew, Jimson, R. Stapenhurst, D. K. Pradhan   +9 more
core   +1 more source

Valosin‐containing protein counteracts ATP‐driven dissolution of FUS condensates through its ATPase activity in vitro

FEBS Letters, EarlyView.
Biomolecular condensates formed by fused in sarcoma (FUS) are dissolved by high ATP concentrations yet persist in cells. Using a reconstituted system, we demonstrate that valosin‐containing protein (VCP), an AAA+ ATPase, counteracts ATP‐driven dissolution of FUS condensates through its D2 ATPase activity.
Hitomi Kimura, Shin‐ichi Tate, Kyota Yasuda   +2 more
wiley   +1 more source

Optimization of the Brillouin operator on the KNL architecture

EPJ Web of Conferences, 2018
Experiences with optimizing the matrix-times-vector application of the Brillouin operator on the Intel KNL processor are reported. Without adjustments to the memory layout, performance figures of 360 Gflop/s in single and 270 Gflop/s in double precision ...
Dürr Stephan
doaj   +1 more source