Results 171 to 180 of about 12,898 (231)
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IEEE Design & Test of Computers, 1986
The goals of the very high speed integrated circuit (or VHSIC) program are to reduce IC design time and effectively insert VHSIC technology into military systems. These goals, indicating the need for a standard means of communication to stream-line advanced digital design and documentation, motivated the development of a hardware description language ...
Allen Dewey, Anthony Gadient
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The goals of the very high speed integrated circuit (or VHSIC) program are to reduce IC design time and effectively insert VHSIC technology into military systems. These goals, indicating the need for a standard means of communication to stream-line advanced digital design and documentation, motivated the development of a hardware description language ...
Allen Dewey, Anthony Gadient
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VHDL-A: analog extension to VHDL
Proceedings Seventh Annual IEEE International ASIC Conference and Exhibit, 2002VHDL is an IEEE standardized language for the description and simulation of digital circuits and systems. Originally developed in the early 1980s, VHDL has achieved great success in electronic design automation, and is emerging as an indispensable tool to deal with complex ASIC system design.
R. Shi +4 more
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IEEE Design & Test of Computers, 1986
The hardware and software communities have reviewed VHDL extensively throughout its conception and development. This follows the 1970s example set during development of the Ada programming language. Analysis of language, like one's preference in clothing, is subjective.
J. Daniel Nash, Larry F. Saunders
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The hardware and software communities have reviewed VHDL extensively throughout its conception and development. This follows the 1970s example set during development of the Ada programming language. Analysis of language, like one's preference in clothing, is subjective.
J. Daniel Nash, Larry F. Saunders
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Proceedings of EURO-DAC 93 and EURO-VHDL 93- European Design Automation Conference, 2002
Previously, the authors (Proc. Euro. Design Automat. Conf., pp. 680-681, 1992) defined how the concept of synchronous design can be mapped to VHDL descriptions. Now, they present a set of rules, such that, if respected, the VHDL description is synchronous. They then extend the strict notion of synchronism to circuits that can be resynchronized assuming
Alain Debreil, Philippe Oddo
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Previously, the authors (Proc. Euro. Design Automat. Conf., pp. 680-681, 1992) defined how the concept of synchronous design can be mapped to VHDL descriptions. Now, they present a set of rules, such that, if respected, the VHDL description is synchronous. They then extend the strict notion of synchronism to circuits that can be resynchronized assuming
Alain Debreil, Philippe Oddo
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Kluwer International Series in Engineering and Computer Science, 1993 An open process of restandardization, conducted by the IEEE, has led to the definitions of the new VHDL standard. The changes make VHDL safer, more portable, and more powerful. VHDL also becomes bigger and more complete.
Jean-Michel Berge +2 more
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IEEE Design & Test of Computers, 2001
Provides a brief overview of VHDL-related standards. The IEEE approved the original VHDL standard (IEEE Std 1076) in 1987, then revised and significantly enhanced it in 1993. In 2000, an interim edition added concurrency control features for shared variables. The new features, called protected types, are based on the idea of monitors seen in concurrent
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Provides a brief overview of VHDL-related standards. The IEEE approved the original VHDL standard (IEEE Std 1076) in 1987, then revised and significantly enhanced it in 1993. In 2000, an interim edition added concurrency control features for shared variables. The new features, called protected types, are based on the idea of monitors seen in concurrent
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VHDL/S — integrating statecharts, timing diagrams, and VHDL
Microprocessing and Microprogramming, 1993Abstract VHDL/S, the language being developed and employed in the FORMAT project, integrates VHDL, temporal logic, and, as graphical formalisms, timing diagrams and state based specifications into a single framework for specification and verification of reactive behaviour, in particular on the system level.
Johannes Helbig +4 more
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Conference proceedings on 27th ACM/IEEE design automation conference - DAC '90, 1990
A validation suite for the IEEE standard VHSIC Hardware Description Language (VHDL) is discussed along with its executive manager. Test points are generated from the VHDL LRM (language reference manual) syntax diagrams and sentences. Each test in the suite contains a test header which is specially formatted and keeps information such as test point ...
James Armstrong +3 more
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A validation suite for the IEEE standard VHSIC Hardware Description Language (VHDL) is discussed along with its executive manager. Test points are generated from the VHDL LRM (language reference manual) syntax diagrams and sentences. Each test in the suite contains a test header which is specially formatted and keeps information such as test point ...
James Armstrong +3 more
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1998 IEEE International Conference on Electronics, Circuits and Systems. Surfing the Waves of Science and Technology (Cat. No.98EX196), 2002
This paper reports on a prototype, network-based virtual laboratory that allows geographically distributed users to share and run existing tools via a standard Web browser. The software infrastructure for the virtual laboratory is described and ongoing application of this infrastructure to digital systems design and education is discussed.
Tania Vassileva +3 more
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This paper reports on a prototype, network-based virtual laboratory that allows geographically distributed users to share and run existing tools via a standard Web browser. The software infrastructure for the virtual laboratory is described and ongoing application of this infrastructure to digital systems design and education is discussed.
Tania Vassileva +3 more
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Experiences with VHDL and FPGAs
Journal of Systems Architecture, 1996Abstract In order to remain competitive,a company needs to reduce its product development time,and consequently the development time for prototyping has to be reduced as well.One way to decrease the development time of a product is to synthesize the design description automatically to FPGAs (Field Programmable Gate Arrays).This article describes the ...
Lennart Lindh +2 more
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