Results 191 to 200 of about 12,898 (231)

?????????????????????? ?????????? VHDL ?????? ???????????????????????????????? ???????????????????? ????????

2008
?????????????????????? ?????????????????????? ?????????? ???????????????? ???????????????????? ?????????????? ?????? ???????????????????????????????? ?????????????????? ??????- ?????????????????????????? ?????????? ?? ?????????????????? ???????????? ?? ?????????? ?? ?????????????????????????? ???????????? ?? ??????????????. ?????????????????? ??????????
openaire   +1 more source

VHDL 1076.1-analog and mixed-signal extensions to VHDL

Proceedings EURO-DAC '96. European Design Automation Conference with EURO-VHDL '96 and Exhibition, 1997
Ernst Christen, Kenneth Bakalar
openaire   +1 more source

Open-Source HW/SW Co-Simulation Using QEMU and GHDL for VHDL-Based SoC Design

Electronics (Switzerland), 2023
Giorgio Biagetti, Laura Falaschetti, Paolo Crippa   +2 more
exaly  

???????????????????? ???????????????????? ???????????? ?????? ???????????????????????????? ?????????????????????? VHDL-???????????????? ???????????????? ??????????????????

2017
?????????????????????? ??????????????????, ?????????????????????? ???? ???????????????????? ?? ???????????????????? ?????????????????????????? ???????????????????????????????????? ?????????????????? ???????????????? ?????????????? ?????????????????????????????? ???????? ?????????????????? ???????????????? ?? ???????????????? ???????????????? ???????? ??
openaire   +1 more source

A Formalisation of the VHDL Simulation Cycle

1993
The VHSIC Hardware Description Language (VHDL) has been gaining wide acceptance as a unifying HDL. It is, however, still a language in which the only way of validating a design is by careful simulation. With the aim of better understanding VHDL's particular simulation process and eventually reasoning about it, we have developed a formalisation of VHDL ...
openaire   +1 more source

???????????????????????????? ?????????????? ?? ?????????????????? ???????????? ???? ???????? ?? ???????????????????????????? ?????????? VHDL

2014
The structural realization of the PLD-based of a Xilinx type FPGA 32-bit module of division with a floating point appropriate to the standard IEEE-754, executed by using the behavioral description of algorithm by language VHDL is offered. The check of functioning of the module of division by a method of modeling in system ModelSim Xilinx Edition???MXE ...
openaire   +1 more source

Parallel VHDL simulation

Proceedings Design, Automation and Test in Europe, 2002
openaire   +2 more sources

VHDL

1998
Petru Eles, Krzysztof Kuchcinski, Zebo Peng   +2 more
openaire   +1 more source

VHDL

2003
Gerhard H. Schildt, Alexander Redlein, Daniela Kahn   +2 more
openaire   +1 more source

A methodology for VLSI implementation of Cellular Automata algorithms using VHDL

Advances in Engineering Software, 2001
Georgios Ch Sirakoulis, Ioannis G Karafyllidis, A Thanailakis   +2 more
exaly