Results 181 to 190 of about 12,898 (231)

VHDL virtual prototyping

Proceedings Sixth IEEE International Workshop on Rapid System Prototyping. Shortening the Path from Specification to Prototype, 2002
Prototyping has been used to develop electronic systems for a long time. In this work a new prototyping approach, that we named VHDL Virtual Prototyping, is introduced. The new approach introduces VHDL models as the hardware part of the system prototype.
Serafín Olcoz, Luis Entrena, Luis Berrojo   +2 more
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Information models of VHDL

Proceedings of the 32nd ACM/IEEE conference on Design automation conference - DAC '95, 1995
The paper discusses issues related to the application of information modelling to the field of Electronic CAD, using VHDL as the basis for discussion. It is shown that an information model of VHDL provides a coherent and uniform description of the VHDL objects at different levels of the language and of the transformations that interrelate these levels.
Cristian A. Giumale, Hilary J. Kahn
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Synthesis from VHDL

Proceedings 1988 IEEE International Conference on Computer Design: VLSI, 2003
The VHDL Synthesis System (VSS) uses VHDL dataflow or behavioral descriptions as input and outputs a structural description of generic components. This structural description is converted into a schematic and captured by the microarchitecture and logic optimization system for technology mapping and constraint-driven optimization.
Joseph Lis, Daniel D. Gajski
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A Polymodal Semantics for VHDL

1997
This paper presents a formal semantics for a subset of VHDL that includes the basic control constructs, delta and unit delay signal assignment, variable assignment, and all forms of wait statements. A polymodal logic with two temporal modalities is used as the underlying formalism, thus allowing for formalization of the flows of time as well as control
Subash Shankar, James R. Slagle
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VHDL's Impact on Test

IEEE Design & Test of Computers, 1986
High-tech microcircuits command a modernized approach to design and test. This approach, born of harsh economic reality, mandates that effective test be inextricably tied to design. The test generation problem is enormous and requires automatic test program generators that in turn require computer-readable descriptions of the unit under test.
Al Lowenstein, Greg Winter
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A flowgraph semantics of VHDL: Toward a VHDL verification workbench in HOL

Formal Methods in System Design, 1995
VHDL-based verification methods require a formalized semantics of this hardware description language. As it has been shown recently that flowgraphs are an excellent means for defining the semantics of VHDL, we also use them to formalize full VHDL. However, our approach differs in important aspects from previous works.
Ralf Reetz, Thomas Kropf
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The state of VHDL in Russia

Proceedings of the 30th international on Design automation conference - DAC '93, 1993
This paper gives an overview of HDL's developed in Russia, from the early 1970s to publication of VHDL in the 1990s. It also chronicles the activities of the Soviet Union VHDL Interest Group (SUVHDLIG), formed in 1990, which consolidated 40 enterprises of the USSR, including universities.
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VHDL - The Designer Environment

IEEE Design & Test of Computers, 1986
Part of the VHDL program is to define a support environment for the VHSIC hardware description language. This support environment is both an open-ended integration framework for what is expected to be a growing list of tools interfaced to VHDL, and a specific set of software which is being implemented in Phase B of the program.
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Deep embedding VHDL

1995
It is shown how a significant subset of VHDL has been deep embedded in HOL along with the four abstraction types of hardware: behavioral, structural, data, temporal.
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Getting started with VHDL

Proceedings of International Conference on Microelectronic Systems Education, 2002
This paper describes a module developed by the author for the initial teaching of VHDL. A 'self-teach' approach is adopted whereby students with a minimum of tutor support can progress from a basic knowledge of digital logic to modelling an ALU in six three hour sessions.
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