Results 41 to 50 of about 39,832 (274)

Bioinspired Fully On‐Chip Learning Implemented on Memristive Neural Networks

Advanced Intelligent Systems, Volume 7, Issue 12, December 2025.
This work proposes a memristive neural network based on van der Waals ferroelectric memristors and contrastive Hebbian learning, enabling fully on‐chip learning. The system achieves over 98% accuracy in pattern recognition with low power consumption (0.321 nJ/image) and high robustness, paving the way for efficient, bioinspired neuromorphic computing ...
Zhixing Wen, Ge Wang, Xiao Luo, Lei Liang, Fan Yang, Xuemei Wang, Qiui Zhang, Jiangang Chen, Qing Liu, Fucai Liu   +9 more
wiley   +1 more source

Semantics and synthesis of signals in behavioral VHDL [PDF]

, 1992
Signals are a fundamental part of VHDL behavioral descriptions. There are many kinds of VHDL signals, each possesing complex and hence often misunderstood semantics. The result is that synthesis tools often inadequately address synthesis of signals.
Gajski, Daniel D., Narayan, Sanjiv, Ramachandran, Loganath, Vahid, Frank   +3 more
core  

Implementation of JPEG compression and motion estimation on FPGA hardware

, 2008
A hardware implementation of JPEG allows for real-time compression in data intensivve applications, such as high speed scanning, medical imaging and satellite image transmission.
Gopalakrishnan, Ramakrishna
core   +1 more source

Timing verification of dynamically reconfigurable logic for Xilinx Virtex FPGA series [PDF]

, 2002
This paper reports on a method for extending existing VHDL design and verification software available for the Xilinx Virtex series of FPGAs. It allows the designer to apply standard hardware design and verification tools to the design of dynamically ...
David Robinson, Eh Bh, Ian Robertson, James Irvine, Patrick Lysaght   +4 more
core   +2 more sources

Generating Logical Architectures from SysML Behavior Models

Systems Engineering, Volume 28, Issue 6, Page 762-778, November 2025.
ABSTRACT Modeling solution‐neutral operating principles of system features as SysML behavior models enable systems engineers to specify reusable product features for a variety of similar products and to specify and document a product's functionality in an easy‐to‐understand manner.
Christian Granrath, Christopher Kugler, Judith Michael, Bernhard Rumpe, Louis Wachtmeister   +4 more
wiley   +1 more source

Topología Daisy Chain en FPGA para modernización naval: implementación y extensión con ARP

Revista Elektrón
Las consolas de operaciones, interfaces de interacción humana implementadas en las Unidades de Superficie del Comando de la Flota Naval, facilitan la visualización de datos críticos y la gestión de sistemas mediante la entrada de comandos por parte de ...
Emiliano Sebastián Gallo, Ricardo Luis Cayssials, Christian Luis Galasso, Alan Emir Arias   +3 more
doaj   +1 more source

Optimization of the symmetric encryption mode ECB dedicated to securing medical data [PDF]

Journal of Electrical and Electronics Engineering, 2021
Data security is a recurring problem to protected the private life of users, Data encryption is necessary but also delicate step to ensure at the same time speed and security of transmission and reception data, there are different models of cryptography ...
SEGHIRI Naouel, BABA-AHMED Mohammed Zakarya, BENMAMMAR Badr   +2 more
doaj  

Structured modeling for VHDL synthesis [PDF]

, 1989
This report will describe a proposed modeling style for the use of the VHSIC Hardware Description Language (VHDL) in design synthesis. We will describe the operations and underlying assumptions of four design models currently understood and used in ...
Gajski, Daniel D., Lis, Joseph S.
core  

Hardware Design for Secure Telemedicine Using A Novel Framework, A New 4D Memristive Chaotic Oscillator, and Dispatched Gray Code Scrambler

Engineering Reports, Volume 7, Issue 10, October 2025.
This work presents a secure telemedicine cryptosystem based on a novel 4D memristive chaotic oscillator and a Dispatched Gray Code Scrambler (DGCS). Implemented on FPGA, the system ensures power‐efficient encryption, making it suitable for real‐time medical image transmission in IoT healthcare environments.
Fritz Nguemo Kemdoum, Serge Raoul Dzonde Naoussi, Gideon Pagnol Ayemtsa Kuete, Justin Roger Mboupda Pone   +3 more
wiley   +1 more source

On the Embedded of a Fast, Light and Robust Chaos‐Based Cryptosystem in NEXYS4 FPGA Card for Real Time Color Image Security (CBC in N‐FPGA‐RTCIP)

Engineering Reports, Volume 7, Issue 9, September 2025.
Security evaluation, NPCR + UACI results of 99.5978% and 33.4549% respectively, confirm the system is secure against statistical and differential attacks. Besides, the FPGA implementation achieves low power of 115 mW at a speed of 42.56 MHz. This makes it suitable for IoT applications where power and hardware resources are constrained. ABSTRACT In this
Fritz Nguemo Kemdoum, Gideon Pagnol Ayemtsa Kuete, Serge Raoul Dzonde Naoussi, Justin Roger Mboupda Pone, Wulfran Fendzi Mbasso   +4 more
wiley   +1 more source