Results 51 to 60 of about 39,832 (274)
Programmable Logic Devices in Experimental Quantum Optics [PDF]
, 2002 We discuss the unique capabilities of programmable logic devices (PLD's) for experimental quantum optics and describe basic procedures of design and implementation.
Andrews +12 more
core +2 more sources
International Journal of Numerical Modelling: Electronic Networks, Devices and Fields, Volume 38, Issue 5, September/October 2025.ABSTRACT In this article, we provide a novel, expanded, and adapted pruning approach for the Simplified Volterra Series (SVS) model that makes it applicable to a wider range of Power Amplifiers (PAs). The proposed Modified SVS (MSVS) model is then applied in a Digital Predistortion (DPD) architecture to linearize a 25 W Gallium Nitride (GaN) RF PA.
Haithem Rezgui +3 more
wiley +1 more source
Journal of Child Psychology and Psychiatry, Volume 66, Issue 5, Page 697-715, May 2025.Background Adolescent mental health is vital for public health, yet many interventions fail to recognise adolescents as proactive community contributors. This paper discusses the co‐design and acceptability testing of a chat‐story intervention to enhance Brazilian adolescents' participation in the promotion of mental health in their peer communities ...
Gabriela Pavarini +56 more
wiley +1 more source
Top-Down Behavioral Modeling Methodology of a Piezoelectric Microgenerator For Integrated Power Harvesting Systems [PDF]
, 2008 In this study, we developed a top/down methodology for behavioral and structural modeling of multi-domain microsystems. Then, we validated this methodology through a study case : a piezoelectric microgenerator.
Basrour, S. +2 more
core +3 more sources
Large scale system design aided by modelling and DES simulation: A Petri net approach
Software: Practice and Experience, Volume 55, Issue 2, Page 243-271, February 2025.Abstract The study of real discrete event systems requires the use of models to cope with complexity and large scale. The only way to understand and analyse their behaviour prior to implementation is, in practice, through distributed simulation. Although it is a widely studied discipline, the difficulty of developing efficient distributed simulation ...
Unai Arronategui +2 more
wiley +1 more source
Obtaining functionally equivalent simulations using VHDL and a time-shift transformation [PDF]
, 1991 The advent of VHDL has brought about a number of VHDL simulators. Many translation schemes from domain specific languages to supposedly functionally equivalent VHDL have been developed as an approach to obtaining simulations.
Vahid, Frank
core +1 more source
A High-level EDA Environment for the Automatic Insertion of HD-BIST Structures [PDF]
, 2000 This paper presents a High-Level EDA environment based on the Hierarchical Distributed BIST (HD-BIST), a flexible and reusable approach to solve BIST scheduling issues in System-on-Chip applications.
Benso, Alfredo +4 more
core +1 more source
EthVault: A Secure and Resource‐Conscious FPGA‐Based Ethereum Cold Wallet
IET Blockchain, Volume 5, Issue 1, January/December 2025.This work presents EthVault, the first hardware‐based Ethereum hierarchical deterministic cold wallet, featuring FPGA implementations of key cryptographic algorithms for secure key generation. A novel ECC architecture resilient to side‐channel and timing attacks, along with an efficient child key derivation function, are introduced. Implementation on a
Joel Poncha Lemayian +3 more
wiley +1 more source
An Approach to Distance Estimation with Stereo Vision Using Address-Event-Representation [PDF]
, 2011 Image processing in digital computer systems usually considers the visual information as a sequence of frames. These frames are from cameras that capture reality for a short period of time.
Cerezuela Escudero, Elena +7 more
core +1 more source
IET Cyber-Physical Systems: Theory &Applications, Volume 10, Issue 1, January/December 2025.This paper introduces an online distributed hardware scheduler that outperforms similar schedulers in terms of performance, predictability, power and energy consumption and temperature management. Implementing the scheduler in hardware results in fewer clock cycles, lower latency and greater efficiency compared to software implementations.
Mohammadreza Saberikia +2 more
wiley +1 more source