Results 61 to 70 of about 22,732 (218)

CRC 8-bit Encoder-Decoder Component in FPGA using VHDL

Jurnal Elkomika, 2020
AbstrakCyclic Redundancy Check (CRC) adalah salah satu jenis dari deteksi kesalahan yang digunakan pada pengiriman data. CRC umumnya digunakan di jaringan digital dan perangkat penyimpanan untuk mendeteksi perubahan tidak disengaja pada data asli.
ANDHI RACHMAN SALEH, SUNNY ARIEF SUDIRO
doaj   +1 more source

VHDL Implementation of 8-Bit ALU

, 2012
In this paper VHDL implementation of 8-bit arithmetic logic unit (ALU) is presented. The design was implemented using VHDL Xilinx Synthesis tool ISE 13.1 and targeted for Spartan device.
Suchita N. Kamble, N. Mhala
semanticscholar   +1 more source

High‐efficiency multilevel inverter topology with minimal switching devices for enhanced power quality and reduced losses

IET Power Electronics, Volume 18, Issue 1, January/December 2025.
In this article, the authors introduced a novel MLI topology in symmetric and asymmetric configurations aiming to attain fewer power electronic devices for synthesizing more steps in the load voltage in contrast with conventional topologies. The proposed topology uses minimal on‐state switching devices leading to a diminution of power loss and voltage ...
Ramesh Jayaraman, Sandirasegarane Thamizharasan, Jeevarathinam Baskaran, Veerpratap Meena, Jitendra Bahadur, Vinay Kumar Jadoun   +5 more
wiley   +1 more source

Agent based online learning approach for power flow control of electric vehicle fast charging station integrated with smart microgrid

IET Renewable Power Generation, Volume 19, Issue 1, January/December 2025.
Abstract In stochastic power systems, electric vehicle (EV) fast charging stations (FCS) are rapidly being installed, while adversely impacts the distribution network. Due to this, the improper offline charging control policies for EVs may increase the voltage fluctuation and instability.
Mohammad Amir, Zaheeruddin, Ahteshamul Haque, V. S. Bharath Kurukuru, Farhad Ilahi Bakhsh, Akbar Ahmad   +5 more
wiley   +1 more source

FPGA‐Based Deep Neural Network Implementation for Handwritten Digit Recognition

Advances in Multimedia, Volume 2025, Issue 1, 2025.
This paper presents a field programmable gate array (FPGA)–based implementation of a deep neural network (DNN) for handwritten digit recognition. We propose the use of a fully connected four‐layer neural network with the hidden layers implementing the ReLU activation function and the output layer based on the Softmax activation function.
Matej Štajnbrikner, Igor Valek, Tomislav Matić, Mario Vranješ, Pramita Mishra   +4 more
wiley   +1 more source

Optimal Design of Battery Energy Storage System Controllers for Damping Low‐Frequency Oscillations

International Journal of Energy Research, Volume 2025, Issue 1, 2025.
Battery energy storage systems (BESSs) have recently been utilized in power systems for various purposes. Integrating these devices into power systems can enhance the damping capability of subsynchronous oscillations. The interaction between the control modes of the BESS and synchronous machines, as well as the control parameters of the BESS, reduces ...
Saeed Hasanvand, Hossein Sobhani, Mohammad Mardaneh, Mohammad-Hassan Khooban, Valaparai Surangani Manikandan   +4 more
wiley   +1 more source

Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

Jurnal Rekayasa Elektrika, 2012
A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others.
. Zulfikar
doaj   +1 more source

Purification and properties of the very high density lipoprotein from the hemolymph of adult Triatoma infestans.

Journal of Lipid Research, 1989
The very high density lipoprotein (VHDL) of Triatoma infestans hemolymph from adult males has been isolated and purified by two-step density gradient ultracentrifugation. It appears to be homogeneous as judged by native polyacrylamide gel electrophoresis.
O J Rimoldi, J L Soulages, S M González, R O Peluffo, R R Brenner   +4 more
doaj   +1 more source

Cloning and expression of the VHDL receptor from fat body of the corn ear worm, Helicoverpa zea

Journal of Insect Science, 2004
In Noctuids, storage proteins are taken up into fat body by receptor-mediated endocytosis. These include arylphorin and a second, structurally unrelated very high-density lipoprotein (VHDL).
Deryck R. Persaud, Norbert H. Haunerland
doaj  

Technology independent optimization when implementing sparse systems of disjunctive normal forms of Boolean functions in ASIC

Informatika
Objectives. The problem of choosing the best methods and programs for circuit implementation as part of digital ASIC (Application-Specific Integrated Circuit) sparse systems of disjunctive normal forms (DNF) of completely defined Boolean functions is ...
P. N. Bibilo, S. N. Kardash
doaj   +1 more source