Results 211 to 220 of about 73,522 (251)

Brain's geometries for movements and beauty judgments. A contribution of topos geometries. [PDF]

Front Psychol
Bennequin D, Berthoz A.
europepmc   +1 more source

Li-Well ZnO Memtransistors: High Reliability for Neuromorphic Applications. [PDF]

Adv Mater
Son KH, Kim HS, Han DH, Lim HK, Lee HS.
europepmc   +1 more source

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3D Flash Memories

Microelectronics Reliability, 2016
This book walks the reader through the next step in the evolution of NAND flash memory technology, namely the development of 3D flash memories, in which multiple layers of memory cells are grown within the same piece of silicon. It describes their working principles, device architectures, fabrication techniques and practical implementations, and ...
Chong Leong Gan, Uda Hashim
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Vertical 3D NAND Flash Memory Technology

ECS Transactions, 2011
We've developed Bit Cost Scalable (BiCS) flash technology as a three-dimensional memory for the future ultra high density storage devices, which extremely reduces the chip costs by vertically stacking memory arrays with punch and plug process. We've advanced it into Pipe-shaped BiCS flash memory introducing U-shaped NAND string structure, to improve ...
Akihiro Nitayama, Hideaki Aochi
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Split-Gate Flash Memory: from Planar to 3D

2021 International Symposium on Electronics and Smart Devices (ISESD), 2021
This review addresses the growth of split-gate flash memory technology, which has matured over the past few decades, and is now entering the domain of non-planar structure. The technology was first introduced as a groundbreaking technology because of its high programming efficiency, low power consumption, over-erase immunity, and superior reliability ...
Zefanya Chandra, Ita Mubarokah, M. Amin Sulthoni   +2 more
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Reprogramming 3D TLC Flash Memory based Solid State Drives

ACM Transactions on Storage, 2022
NAND flash memory-based SSDs have been widely adopted. The scaling of SSD has evolved from plannar (2D) to 3D stacking. For reliability and other reasons, the technology node in 3D NAND SSD is larger than in 2D, but data density can be increased via increasing bit-per-cell.
Congming Gao, Min Ye, Chun Jason Xue, Youtao Zhang, Liang Shi, Jiwu Shu, Jun Yang   +6 more
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3D AND: A 3D Stackable Flash Memory Architecture to Realize High-Density and Fast-Read 3D NOR Flash and Storage-Class Memory

2020 IEEE International Electron Devices Meeting (IEDM), 2020
We demonstrate a 3D stackable AND-type Flash memory architecture for high-density and fast-read non-volatile memory solution. The device is based on a gate-all-around (GAA) macaroni thin-body device, with two vertical buried diffusion lines by N+ doped poly plug to connect all memory cells in a parallel way to achieve 3D AND-type array.
Hang-Ting Lue, Guan-Ru Lee, Teng-Hao Yeh, Tzu-Hsuan Hsu, Chieh Roger Lo, Cheng-Lin Sung, Wei-Chen Chen, Chia-Tze Huang, Kuan-Yuan Shen, Meng-Yen Wu, Pishan Tseng, Min-Feng Hung, Chia-Jung Chiu, Kuang-Yeu Hsieh, Keh-Chung Wang, Chih-Yuan Lu   +15 more
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Disturbance Relaxation for 3D Flash Memory

IEEE Transactions on Computers, 2016
Even though 3D flash memory presents a grand opportunity to huge-capacity non-volatile memory, it suffers from serious program disturbance problems. In contrast to the past efforts in error correction codes and the work in trading the space utilization for reliability, we propose a disturbance-relaxation scheme that can alleviate the negative effects ...
Yu-Ming Chang, Yuan-Hao Chang, Tei-Wei Kuo, Yung-Chun Li, Hsiang-Pang Li   +4 more
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Characteristics of Junctionless Charge Trap Flash Memory for 3D Stacked NAND Flash

Journal of Nanoscience and Nanotechnology, 2013
The electrical characteristics of tunnel barrier engineered-charge trap flash (TBE-CTF) memory devices with junctionless (JL) source and drain (S/D) were investigated. The JL structure is composed of an n(+)-poly-Si based ultra-thin channel and S/D with identical doping concentrations.
Jinho, Oh, Heedo, Na, Sunghoon, Park, Hyunchul, Sohn   +3 more
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3D-NAND Flash memory and technology

2019
This chapter introduces the design of three-dimensional (3D) NAND flash memory with the implications from the system side. For conventional two-dimensional (2D) scaling, it is facing various limitations such as lithography cost and cell-to-cell coupling interference. To sustain the trend of bit-cost reduction beyond 10 nm technology node, 3D NAND flash
Chao Sun, Ken Takeuchi
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