Results 191 to 200 of about 1,500,059 (236)

Utilizing PFIB for Preparing TEM Lamellae Tailored to High Aspect Ratio 3D NAND Structures

International Symposium for Testing and Failure Analysis
The TEM sample preparation by Plasma focused ion beam (PFIB) for a 3D NAND sample with high aspect ratio (HAR) was investigated. Through the PFIB window delayering method, a nearly curtain-free and uniform thickness of TEM lamella could be obtained ...
Yu-Chih Chen, Zhao-Ling Wu, Bo-Hao Chiou, Chun-Hung Lin, Hsin-Cheng Hsu, C. Yeh, N. Lian, Ta-Hone Yang, Kuang-Chao Chen   +8 more
semanticscholar   +1 more source

NAND-Tree: A 3D NAND Flash Based Processing in Memory Accelerator for Tree-Based Models on Large-Scale Tabular Data

International Conference on Computer Aided Design
Tabular data are a widely used format in data science, and treebased Machine Learning (ML) models are powerful tools and outperform Deep Neural Network (DNN) with higher accuracy for tasks on tabular data.
Hongtao Zhong, Taixin Li, Yiming Chen, Wenjun Tang, Juejian Wu, Huazhong Yang, Xueqing Li   +6 more
semanticscholar   +1 more source

LA-Write: Balancing Endurance of Inter-Layer for Prolonging 3D NAND Flash Memory Lifetime

IEEE International Conference on Networking, Architecture and Storages
With vertical stacking, 3D NAND flash memory can achieve continuous capacity growth. However, as the number of stacked layers in a flash block increases, the endurance variation between the stacked layers becomes more and more significant due to process ...
Yu Wan, Yajuan Du, Siyi Huang
semanticscholar   +1 more source

Opportunities and challenges of 3D NAND scaling

2013 International Symposium on VLSI Technology, Systems and Application (VLSI-TSA), 2013
3D NAND is attracting increasing attention as a NAND scaling solution. In 3D NAND, the physical cell size is decoupled from the effective cell size by stacking multiple tiers. This enables effective NAND cell size scaling without degrading cell performance and reliability. However, 3D process integration could introduce new sources of cell degradation.
openaire   +1 more source

Comprehensive Charaterizations on Read Disturbs in QLC Charge-Trap (CT) 3D NAND Flash

IEEE International Conference on Solid-State and Integrated Circuit Technology
To address the concern of serious read disturb (RD) in 3D NAND flash with lateral charge migration (LCM), Quad-level-cell (QLC) Charge-trap (CT) type 3D NAND flash memory is characterized systematically on a NAND chip tester, including the properties of ...
Shaoqi Yang, Xiaohuan Zhao, Peng Guo, Qianwen Wang, Guangkuo Yang, Xinyi Guo, Pengpeng Sang, Jixuan Wu, Xuepeng Zhan, Jiezhi Chen   +9 more
semanticscholar   +1 more source

3D-NAND Flash and Its Manufacturing Process

2016
Flash memory chips are nonvolatile memory (NVM) chips, which can keep memory without power supply. In comparison, DRAM is volatile memory and needs a power supply. Flash memory chips, especially NAND flash memory chips, are commonly used in universal serial bus (USB) drives, secure digital (SD) cards, and SSDs.
openaire   +1 more source

On the Accurate and Robust Prediction of Optimal Read Voltages in 3D NAND via Data Augmentation

2024 4th International Conference on Intelligent Technology and Embedded Systems (ICITES)
With the exponential growth of data, the demand for storage capacity is constantly increasing, leading to the widespread adoption of 3D NAND flash memory in enterprise storage and data centers.
Guanyu Wu, Xiangyu Yao, Yu Chen, Qiao Li, Jie Zhang, C. Xue   +5 more
semanticscholar   +1 more source

3D X-DRAM: A Novel 3D NAND-like DRAM Cell and TCAD Simulations

International Memory Workshop
This paper presents a novel capacitorless 3D DRAM floating body cell using a 3D NAND-like cell structure known as 3D X-DRAM. This allows the cells to be manufactured using the mature 3D NAND process with minor changes to reduce the challenges in ...
Fu-Chang Hsu, Richard J. Huang, Re-Peng Tsay, Jui-Hsin Chang, Chia-Haur Chang, I-Wei Huang, Kevin Hsu   +6 more
semanticscholar   +1 more source

Current Status of NAND Memories and its Future Prospect with 3D NAND Technology

ECS Meeting Abstracts, 2012
Abstract not Available.
openaire   +1 more source

Penta-Level Charge Trap-Based 3D NAND Flash Memory Enabled by Bi-Directional Step-Pulse-Programming and Improvement of Cell Channel Process

International Electron Devices Meeting
We present PLC (Penta-level cell, 5 bits/cell) NAND flash memory using 3D charge-trap-flash (CTF) cell. To achieve PLC cell distribution with proper cell read margin, program noise and short-term data retention (STDR) are addressed as most challenging ...
Changhyun Lee, Dengtao Zhao, Kyeongran Yoo, M. T. Sharbati, P. Htet, Yunsu Kim, Bongyeol Park, Hansoo Joo, Hyeokjun Choi, Soonok Seo, Dawon Kim, Jaewoong Kim, Taeun Youn, Insu Park, J. Sim, Seongjo Park, Sungtaeg Kang, Jungdal Choi   +17 more
semanticscholar   +1 more source