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Wafer Thinning and Dicing Technology for 3D Nand Flash

2019 China Semiconductor Technology International Conference (CSTIC), 2019
It is a main stream for 3-dimensional (3D) NAND flash which has the advantage of large storage capacity, excellent and reliable performance. Several different wafer architectures for 3D NAND flash including BICS (Bit Cost Scalable), TACT (Terabit Cell Array Transistor) and VG (Vertical Gate) etc. are all in mass production mode in current market. These
Qian Ma   +3 more
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3D VG-Type NAND Flash Memories

2016
The common feature among the different 3D NAND solutions is constituted by very deep vertical (z direction) etching steps that define the Flash cells geometries simultaneously. Transistor geometries are formed by the deep trench through a multiple polysilicon/oxide stack.
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Trends and Future Challenges of 3D NAND Flash Memory

2023 IEEE International Memory Workshop (IMW), 2023
Sun Il Shim   +2 more
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Introduction to 3D NAND Flash Memories

2022
Rino Micheloni   +2 more
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Scaling Perspectives on 3D NAND Flash

Extended Abstracts of the 2022 International Conference on Solid State Devices and Materials, 2022
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Layer-to-Layer Endurance Variation of 3D NAND Flash Memory

2022 IEEE International Reliability Physics Symposium (IRPS), 2022
Md Raquibuzzaman   +3 more
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Reliability of 3D NAND Flash for Future Storage Systems (Invited)

2023 IEEE International Reliability Physics Symposium (IRPS), 2023
Akira Goda   +2 more
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Enabling 3D NAND Trench Cells for Scaled Flash Memories

2023 IEEE International Memory Workshop (IMW), 2023
S. Rachidi   +8 more
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Accelerating Sub-Block Erase in 3D NAND Flash Memory

2021 IEEE 39th International Conference on Computer Design (ICCD), 2021
Hongbin Gong, Zhirong Shen, Jiwu Shu
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A DTCO Framework for 3D NAND Flash Readout

2024 Design, Automation & Test in Europe Conference & Exhibition (DATE)
Mattia Gerardi   +6 more
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