Hafnium-Based Ferroelectric Post-Moore Electronics: Device Physics, Integration Architectures, and Neuromorphic System Implementation. [PDF]
Chen X, Wang Z, Meng J, Wang T.
europepmc +1 more source
A full-featured 2D flash chip enabled by system integration. [PDF]
Liu C +13 more
europepmc +1 more source
Band and Field Coengineered Charge Trap Memristor via Au Nanoparticle Layer for Programming Speed Enhancement. [PDF]
Kim G +6 more
europepmc +1 more source
Recent advances in ferroelectric materials, devices, and in-memory computing applications. [PDF]
Hwang H, Youn S, Kim H.
europepmc +1 more source
A Novel Channel Preparation Scheme to Optimize Program Disturbance in Three-Dimensional NAND Flash Memory. [PDF]
You K, Jin L, Jia J, Huo Z.
europepmc +1 more source
Ferroelectric Hafnium Oxide for In-Memory Computing: Advancing Devices, Circuit Architectures, and System-Level Integration. [PDF]
He C, Li W, Li J, Li Q, Xie Z, Du T.
europepmc +1 more source
Design of Low-Latency Layered Normalized Minimum Sum Low-Density Parity-Check Decoding Based on Entropy Feature for NAND Flash-Memory Channel. [PDF]
Li Y, Hu H.
europepmc +1 more source
Characterizing 3D Floating Gate NAND Flash
As both NAND flash memory manufacturers and users are turning their attentions from planar architecture towards three-dimensional (3D) architecture, it becomes critical and urgent to understand the characteristics of 3D NAND flash memory. These characteristics, especially those different from planar NAND flash, can significantly affect design choices ...
Fei Wu, Qin Xiong, Zhonghai Lu
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Trends and Future Challenges of 3D NAND Flash Memory
2023 IEEE International Memory Workshop (IMW), 2023Jaihyuk Song
exaly +2 more sources
Nowadays, Solid State Drives consume an enormous amount of NAND Flash memories [1] causing a restless pressure on increasing the number of stored bits per mm2. Planar memory cells have been scaled for decades by improving process technology, circuit design, programming algorithms [2], and lithography.
Rino Micheloni +2 more
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