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3D Charge Trap NAND Flash Memories
ECS Transactions, 2016This chapter starts off with 2 vertical channel architectures named BiCS (Bit Cost Scalable) and P-BiCS (Pipe-Shaped BiCS), respectively. BiCS was proposed for the first time by Toshiba in 2007, and another version called P-BiCS was presented in 2009 to improve retention, source selector performances and source line resistance.
Luca Crippa, Rino Micheloni
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2018
Nowadays, Solid State Drives consume an enormous amount of NAND Flash memories [1] causing a restless pressure on increasing the number of stored bits per mm2. Planar memory cells have been scaled for decades by improving process technology, circuit design, programming algorithms [2], and lithography.
Rino Micheloni +2 more
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Nowadays, Solid State Drives consume an enormous amount of NAND Flash memories [1] causing a restless pressure on increasing the number of stored bits per mm2. Planar memory cells have been scaled for decades by improving process technology, circuit design, programming algorithms [2], and lithography.
Rino Micheloni +2 more
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3D RRAM design and benchmark with 3d NAND FLASH
2014 12th IEEE International Conference on Solid-State and Integrated Circuit Technology (ICSICT), 2014The monolithic 3D integration of resistive switching random access memory (RRAM) is one attractive approach to build high-density non-volatile memory. In this paper, the design considerations of 3D vertical RRAM architecture are presented from the device, circuit to system level. Due to the voltage drop and sneak path problem, the sub-array size of the
Pai-Yu Chen +3 more
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Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 20213D NAND flash memory faces unprecedented complicated interference than planar NAND flash memory, resulting in more concern regarding reliability and performance. Stronger error correction code (ECC) and adaptive reading strategies are proposed to improve the reliability and performance taking a threshold voltage (V th ) distribution model as the ...
Weihua Liu +7 more
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Characterization of Inter-Cell Interference in 3D NAND Flash Memory
IEEE Transactions on Circuits and Systems I: Regular Papers, 2021We characterize inter-cell interference in commercial three-dimensional NAND flash memory. By writing random data into 3D NAND and collecting sample means and sample variances of cell values corresponding to a particular set of input values in fixed relative neighboring cell locations, it is shown that the interference coming from any target cell ...
Sukkwang Park, Jaekyun Moon
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Characterizing 3D Floating Gate NAND Flash
Proceedings of the 2017 ACM SIGMETRICS / International Conference on Measurement and Modeling of Computer Systems, 2017In this paper, we characterize a state-of-the-art 3D floating gate NAND flash memory through comprehensive experiments on an FPGA platform. Then, we present distinct observations on performance and reliability, such as operation latencies and various error patterns. We believe that through our work, novel 3D NAND flash-oriented designs can be developed
Qin Xiong +7 more
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3D Stacked NAND Flash Memories
2016Market request for bigger and cheaper NAND Flash memories triggers continuous research activity for cell size shrinkage. For many years, workarounds for all the scalability issues of planar Flash memories have been found. Some examples are the improved programming algorithms for controlling electrostatic interference between adjacent cells [6], and the
Rino Micheloni, Luca Crippa
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Reliability challenges in 3D NAND Flash memories
2019 IEEE 11th International Memory Workshop (IMW), 2019The reliability of 3D NAND Flash memory technology is depending on many factors. Most of them are related to the process-induced variability of the layers. Endurance, data retention capabilities, and cross-temperature immunity are the metrics that become affected by this, turning in peculiar reliability challenges that are difficult to be tackled ...
Zambelli C., Micheloni R., Olivo P.
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Reliability of 3D NAND Flash Memories
2016In this chapter the main reliability mechanisms affecting 3D NAND memories will be addressed, providing a comparison between 3D FG and 3D CT devices in terms of reliability and expected performances. Starting from an analysis of basic reliability issues related to both physical and architectural aspects affecting NAND memories, the specific physical ...
GROSSI, Alessandro +2 more
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Etch Challenges for 3D NAND Flash Technology
ECS Meeting Abstracts, 2014Current 2D NAND scaling is approaching technology limitation in both lithography and device performance arena. To address the lithography challenges at the 1x nodes and the well-known scaling issues associated with planar NAND, 3D flash technology is being developed and is expected to greatly reduce the lithography burden albeit shifting it to ...
Anisul Haque Khan +4 more
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