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Atmospheric Neutron Soft Errors in 3-D NAND Flash Memories
IEEE Transactions on Nuclear Science, 2019The sensitivity of vertical-channel 3-D NAND flash memories to wide-energy spectrum neutrons was investigated. The effects of neutron exposure on a 3-D floating gate (FG) cells were studied in terms of threshold voltage shifts and raw bit error rates. The neutron failure rates obtained in the accelerated tests were extrapolated to field conditions at ...
M. Bagatin +5 more
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3D Charge Trap NAND Flash Memories
ECS Transactions, 2016This chapter starts off with 2 vertical channel architectures named BiCS (Bit Cost Scalable) and P-BiCS (Pipe-Shaped BiCS), respectively. BiCS was proposed for the first time by Toshiba in 2007, and another version called P-BiCS was presented in 2009 to improve retention, source selector performances and source line resistance.
Luca Crippa, Rino Micheloni
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Microscopic Physical Origin of Charge Traps in 3D NAND Flash Memories
Extended Abstracts of the 2022 International Conference on Solid State Devices and Materials, 2022Abstract We performed the first-principles calculations for a nitrogen vacancy (V N) and hydrogen(H) atom in β-Si3N4 to clarify the atomistic origin of charge traps in silicon nitride (SiN) layers and charge-trapping mechanism used for 3D NAND flash memories.
Fugo Nanataki +5 more
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Reliability challenges in 3D NAND Flash memories
2019 IEEE 11th International Memory Workshop (IMW), 2019The reliability of 3D NAND Flash memory technology is depending on many factors. Most of them are related to the process-induced variability of the layers. Endurance, data retention capabilities, and cross-temperature immunity are the metrics that become affected by this, turning in peculiar reliability challenges that are difficult to be tackled ...
Zambelli C., Micheloni R., Olivo P.
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Modeling of Threshold Voltage Distribution in 3D NAND Flash Memory
2021 Design, Automation & Test in Europe Conference & Exhibition (DATE), 20213D NAND flash memory faces unprecedented complicated interference than planar NAND flash memory, resulting in more concern regarding reliability and performance. Stronger error correction code (ECC) and adaptive reading strategies are proposed to improve the reliability and performance taking a threshold voltage (V th ) distribution model as the ...
Weihua Liu +7 more
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Characteristics of Junctionless Charge Trap Flash Memory for 3D Stacked NAND Flash
Journal of Nanoscience and Nanotechnology, 2013The electrical characteristics of tunnel barrier engineered-charge trap flash (TBE-CTF) memory devices with junctionless (JL) source and drain (S/D) were investigated. The JL structure is composed of an n(+)-poly-Si based ultra-thin channel and S/D with identical doping concentrations.
Jinho, Oh +3 more
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2018
Nowadays, Solid State Drives consume an enormous amount of NAND Flash memories [1] causing a restless pressure on increasing the number of stored bits per mm2. Planar memory cells have been scaled for decades by improving process technology, circuit design, programming algorithms [2], and lithography.
Rino Micheloni +2 more
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Nowadays, Solid State Drives consume an enormous amount of NAND Flash memories [1] causing a restless pressure on increasing the number of stored bits per mm2. Planar memory cells have been scaled for decades by improving process technology, circuit design, programming algorithms [2], and lithography.
Rino Micheloni +2 more
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3D Stacked NAND Flash Memories
2016Market request for bigger and cheaper NAND Flash memories triggers continuous research activity for cell size shrinkage. For many years, workarounds for all the scalability issues of planar Flash memories have been found. Some examples are the improved programming algorithms for controlling electrostatic interference between adjacent cells [6], and the
Rino Micheloni, Luca Crippa
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Vertical-channel stacked array (VCSTAR) for 3D NAND flash memory
2011 International Semiconductor Device Research Symposium (ISDRS), 2011Abstract A novel three-dimensional (3D) NAND flash memory, VCSTAR (Vertical-Channel STacked ARray), is investigated. The proposed device is a vertical channel structure having stacked word-lines to achieve high memory density without shrinking cell channel length.
Se Hwan Park +4 more
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