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A cell current compensation scheme for 3D NAND FLASH memory
2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015The 3D NAND, so-called vertical NAND has cell Vt degradation especially in low temperature, and it affects cell Vt distribution and shift when NAND operates. To solve this problem, the temperature compensation scheme by ATS(Analog Temp Sensor) using CTAT circuit has proposed.
SungWook Choi +7 more
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Error Generation for 3D NAND Flash Memory
2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022Weihua Liu +4 more
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3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array
IEICE Transactions on Electronics, 2009We propose a 3-dimensional terraced NAND flash memory. It has a vertical channel so it is possible to make a long enough channel in 1F 2 size. And it has 3-dimensional structure whose channel is connected vertically along with two stairs. So we can obtain high density as in the stacked array structure, without silicon stacking process.
Yoon KIM +6 more
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7.7 A 768Gb 3b/cell 3D-floating-gate NAND flash memory
2016 IEEE International Solid-State Circuits Conference (ISSCC), 2016A planar floating-gate NAND technology has previously realized a 0.87Gb/mm2 memory density using 3b/cell [1] and achieved a minimum feature size for 16nm [2]. However, the development of planar NAND flash is expected to reach the scaling limit in a few technology generations.
Tomoharu Tanaka +60 more
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Advanced Architectures for 3D NAND Flash Memories with Vertical Channel
2016One of the key metrics to benchmark different 3D architectures is the storage density, which is here indicated with Bit_Density. Given a specific Flash memory die, this density is defined as the ratio between the storage capacity of the die, Die_Capacity, and its silicon area, Die_Size. In this chapter we present some of the most advanced architectures
Luca Crippa, Rino Micheloni
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Multilevel In-Memory-Searching in 3D NAND-Flash Memory
Extended Abstracts of the 2022 International Conference on Solid State Devices and Materials, 2022Po Hao Tseng +9 more
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Accelerating Sub-Block Erase in 3D NAND Flash Memory
2021 IEEE 39th International Conference on Computer Design (ICCD), 2021Hongbin Gong, Zhirong Shen, Jiwu Shu
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Improving 3D NAND Flash Memories Reliability: a Cross-Layer Perspective
2024 IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA)The 3D NAND Flash memory technology is the main building block of storage architectures such as multimedia cards and Solid-State Drives. Applications ranging from mobile to high-performance computing are continuously calling for an increased storage density, requiring massive scaling efforts at the device and array level.
Zambelli C., Micheloni R.
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Trends and Future Challenges of 3D NAND Flash Memory
2023 IEEE International Memory Workshop (IMW), 2023Sun Il Shim, Jaehoon Jang, Jaihyuk Song
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