Results 121 to 130 of about 2,098 (165)

Study on cell shape in 3D NAND flash memory

2015 IEEE International Conference on Electron Devices and Solid-State Circuits (EDSSC), 2015
All kinds of cell structures are appeared in 3D NAND flash technologies and all seem to be promising. In this paper, detail comparisons among the cell structures of them are presented. The theoretical derivation and simulation results both support that the cylindrical cell structure has better program/erase speed and memory window.
Wei Feng, Nine Deng
openaire   +1 more source

Secondary Particles Generated by Protons in 3-D nand Flash Memories

IEEE Transactions on Nuclear Science, 2022
We studied the secondary byproducts created by high-energy protons inside an SEU detector based on 3D NAND Flash memories, extending the previously developed methodology used for detecting heavy ions. The radiation response of the SEU monitor was discussed as a function of proton energy, analyzing parameters such as the number of clusters per particle,
M. Bagatin, S. Gerardin, A. Paccagnella, A. Costantino, V. Ferlet-Cavrois, G. Santin, M. Muschitiello, A. Pesce, S. Beltrami   +8 more
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Atmospheric Neutron Soft Errors in 3-D NAND Flash Memories

IEEE Transactions on Nuclear Science, 2019
The sensitivity of vertical-channel 3-D NAND flash memories to wide-energy spectrum neutrons was investigated. The effects of neutron exposure on a 3-D floating gate (FG) cells were studied in terms of threshold voltage shifts and raw bit error rates. The neutron failure rates obtained in the accelerated tests were extrapolated to field conditions at ...
M. Bagatin, S. Gerardin, A. Paccagnella, S. Beltrami, C. Cazzaniga, C. D. Frost   +5 more
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Optimization of Performance and Reliability in 3D NAND Flash Memory

IEEE Electron Device Letters, 2020
3D NAND Flash with high storage capacity is in great demand for several technologies, which requires high performance and good reliability at the same time. Therefore, it is proposed to adjust the tunnel layer by changing the first SiO2 (O1) layer thickness near poly Si channel in the tunnel layer based on SiO2/SiOxNy/SiO2 structure.
Yingjie Ouyang, Zhiliang Xia, Tao Yang, Dandan Shi, Wenxi Zhou, Zongliang Huo   +5 more
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3D VG-Type NAND Flash Memories

2016
The common feature among the different 3D NAND solutions is constituted by very deep vertical (z direction) etching steps that define the Flash cells geometries simultaneously. Transistor geometries are formed by the deep trench through a multiple polysilicon/oxide stack.
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Natural Local Self-Boosting Effect in 3D NAND Flash Memory

IEEE Electron Device Letters, 2017
This letter examined the natural local self-boosting effect of an inhibited channel in three-dimensional (3D) NAND flash memory. The inhibited channel in the 3D NAND flash structure can be in the floating state easily, because its channel is not connected directly to its substrate.
Myounggon Kang, Yoon Kim
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FPGA-based reliability testing and analysis for 3D NAND flash memory

Microelectronics Reliability, 2020
Abstract In this article, we described a FPGA-based NAND flash memory hardware and software collaborative design experimental platform. Our novel experimental platform implements timing control and error feature extraction of NAND flash memory, equipped with a computer software based on LabVIEW.
Debao Wei, Zhelong Piao, Hua Feng, Liyan Qiao, Xiyuan Peng   +4 more
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A cell current compensation scheme for 3D NAND FLASH memory

2015 IEEE Asian Solid-State Circuits Conference (A-SSCC), 2015
The 3D NAND, so-called vertical NAND has cell Vt degradation especially in low temperature, and it affects cell Vt distribution and shift when NAND operates. To solve this problem, the temperature compensation scheme by ATS(Analog Temp Sensor) using CTAT circuit has proposed.
SungWook Choi, KyuTae Park, Marco Passerini, HeeJoung Park, DoYoung Kim, ChiHyun Kim, KunWoo Park, JinWoong Kim   +7 more
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Error Generation for 3D NAND Flash Memory

2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 2022
Weihua Liu, Fei Wu, Songmiao Meng, Xiang Chen, Changsheng Xie   +4 more
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3-Dimensional Terraced NAND (3D TNAND) Flash Memory-Stacked Version of Folded NAND Array

IEICE Transactions on Electronics, 2009
We propose a 3-dimensional terraced NAND flash memory. It has a vertical channel so it is possible to make a long enough channel in 1F 2 size. And it has 3-dimensional structure whose channel is connected vertically along with two stairs. So we can obtain high density as in the stacked array structure, without silicon stacking process.
Yoon KIM, Seongjae CHO, Gil Sung LEE, Il Han PARK, Jong Duk LEE, Hyungcheol SHIN, Byung-Gook PARK   +6 more
openaire   +1 more source