Results 121 to 130 of about 993 (140)
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A novel ADPLL design using successive approximation frequency control
Microelectronics Journal, 2009This paper presents a hardware implementation of a fully synthesizable, technology-independent clock generator. The design is based on an ADPLL architecture described in VHDL and characterized by a digital controlled oscillator with high frequency resolution and low jitter.
H. Eisenreich +4 more
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A Low Jitter ADPLL for Mobile Applications
IEICE Transactions on Electronics, 2005This paper describes an ADPLL (All Digital Phase-Locked Loops) with a small DCO (Digitally Controlled Oscillator), low jitter, fine resolution and wide lock range suitable for mobile appplications. The novel DCO circuit is controlled by digital control codes with thermometer type instead of previous binary weighted type.
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Ultra-low phase noise ADPLL for millimeter wave
2020Millimeter-wave (mm-wave) frequency synthesizers in complementary metal oxide-semiconductor (CMOS) suffer from poor phase noise (PN), limited tuning range (TR) and high-power consumption. They are the key subsystems that typically limit the performance of mm-wave transceivers.
Zong, Zhirui, Staszewski, Robert Bogdan
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A Fast-Locking ADPLL with Time Measurable DCO
Advanced Materials Research, 2012This paper proposes a new all digital phase-locked loop (ADPLL) which operates from 80MHz to 800MHz with the locking cycle of less than 40 clock cycles. It employs a time measurable digital controlled oscillator (TMDCO), which helps the reduction of locking cycle.
Tae Ho Lim +3 more
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Phase Noise Simulation and Modeling of ADPLL by SystemVerilog
2008 IEEE International Behavioral Modeling and Simulation Workshop, 2008Event driven phase noise simulation and modeling of an ADPLL by SystemVerilog is presented in this paper. It uses the simple Stochastic Voss-McCartney algorithm to generate the pink noise so that the 1/f phase noise effect can be easily modeled. Since the event driven simulation is extremely fast compared to the circuit level simulation, it allows ...
Tingjun Wen, Tad Kwasniewski
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Low jitter ADPLL insensitive to power supply noise
2010 IEEE International Conference on Industrial Technology, 2010In this paper an analytical method is presented for estimating the timing jitter of ADPLL due to power supply noise. It leads to the conclusion that jitter heavily depends on the power supply noise frequency and the loop gain. Based on the analytical method, a synthesizable ADPLL with good power supply noise rejection is fabricated in SMIC 0.13µm ...
Xiaoying Deng, Jun Yang, Jianhui Wu
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True random number generation from bang-bang ADPLL jitter
2016 IEEE Nordic Circuits and Systems Conference (NORCAS), 2016In this work a concept for true random number generator from jitter in bang-bang ADPLLs within systems-on-chip is presented. For this purpose the phase-frequency detector (PFD) output of an existing ADPLL clock generator bit is directly used as entropy source with zero power and chip area overhead.
Neumarker, Felix +3 more
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Built-In Speed Grading with a Process-Tolerant ADPLL
16th Asian Test Symposium (ATS 2007), 2007Speed grading has becoming more and more important for nanometer technologies to support activities like process monitoring or performance diagnosis. In this work, we analyze the feasibility of providing such a capability through on-chip circuitry.
Hsuan-Jung Hsu +2 more
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A Framework for Automatic Generation of Fully Synthesizable ADPLL
2018 25th IEEE International Conference on Electronics, Circuits and Systems (ICECS), 2018We propose a framework that can generate all digital PLL (ADPLL) from the design specifications. It uses double loop edge injection type ADPLL[1] with phase interpolation oscillator. A calibration logic to correct errors of two oscillators is introduced based on [1].
Shinya Ubukata, Satoshi Komatsu
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The FPGA implement of ADPLL without retimed clock
2011 IEEE International Conference on Anti-Counterfeiting, Security and Identification, 2011A modified method to evaluate the phase of all digital phase-locked loop (ADPLL) output signal is proposed in this paper for improving the robustness property of the loop. The reference clock is used throughout the system as the synchronous clock, which can avoid the metastable output and the injection spurs caused by retiming mechanism, and ...
null Shuai Jiang +2 more
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