Results 1 to 10 of about 84,601 (236)
IEEE Access, 2021 This paper presents a 0.46 mW and 2.4 GHz; All-Digital Phase-Locked Loop (ADPLL) through an Injection-Locked Frequency Multiplier (ILFM) and Continuous Frequency Tracking Loop (CFTL) circuitry for low power Internet-of-Thing (IoT) applications.
Muhammad Riaz Ur Rehman +14 more
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An All-Digital Optical Phase-Locked Loop Suitable for Satellite Downlinks
Photonics, 2023 The optical signal propagation used in satellite uplinks and downlinks is influenced by absorption, scattering, and changes in the atmospheric refractive index or turbulence, causing optical signal attenuation.
Jognes Panasiewicz +4 more
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IEEE Access, 2021 An all-digital phase-locked loop (ADPLL) with a multiphase digitally controlled oscillator (DCO) incorporating the bootstrapped and interpolated schemes is proposed in this paper.
Jen-Chieh Liu, Yu-Ping Li
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All digital phase-locked loop / Visiškai skaitmeninė fazės derinimo kilpa
Mokslas: Lietuvos Ateitis, 2013 The paper reviews working principles of phase-locked loop and drawbacks of classical PLL structure in nanometric technologies. It is proposed to replace the classical structure by all-digital phase-locked loop structure. Authors described the main blocks
Marijan Jurgo
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Realization of an All-Digital Phase-Locked Loop
INTERANTIONAL JOURNAL OF SCIENTIFIC RESEARCH IN ENGINEERING AND MANAGEMENTAn all-digital phase locked loop (PLL) is presented in the paper. The goal of a PLL, a closed-loop control system, is to synchronize the phase and frequency of an incoming signal. Clock generation and recovery communication systems are the most flexible uses of PLL. Digital PLLs are chosen because of the greater integration of digital designs.
Mrs. Shyamala S C +4 more
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, 2013 The paper reviews working principles of phase-locked loop and drawbacks of classical PLL structure in nanometric technologies. It is proposed to replace the classical structure by all-digital phase-locked loop structure. Authors described the main blocks of all-digital phase-locked loop (time to digital converter and digitally controlled oscillator ...
Marijan Jurgo
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Design of All-digital Phase-locked Loop
Problems of advanced micro- and nanoelectronic systems development, 2021 R. Khalirbaginov, Milandr
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Design of All Digital Phase Locked Loop for Wireless Applications
International Journal of Engineering & Technology, 2018 This paper presents a design of All Digital Phase Locked Loop (ADPLL) for wireless applications. It is designed using master and slave Dflipflop for linear phase detector, counter based loop filter and ring oscillator based Digital controlled oscillator(DCO).
Swetha R, J Manjula, A Ruhan bevi
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Design and verification of data acquisition clock circuit based on dual-loop phase-locked loop
He jishu, 2022 Background Digital measurement system based on ADCs (analog-to-digital converter) has higher requirement on the signal to noise ratio (SNR) of sampled data. Among all the factors, the jitter of sampling clock has the most prominent effect on SNR.
LIU Zhi +11 more
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A Novel Design of Hilbert Huang Based All Digital Phase Locked Loop Using FPGA
International Journal of Electrical and Electronic Engineering & Telecommunications, 2023 Many applications for digital processing are steadily increasing in radio frequency signal processing from analog to digital. ADPLL plays a vital role in digital signal processing. Several ADPLL models were introduced in the past.
Velamarthi Spandana, C. Paidimarry
semanticscholar +1 more source