Results 91 to 100 of about 84,601 (236)
Steady-state probability density function of the phase error for a DPLL with an integrate-and-dump device [PDF]
The steady-state behavior of a particular type of digital phase-locked loop (DPLL) with an integrate-and-dump circuit following the phase detector is characterized in terms of the probability density function (pdf) of the phase error in the loop ...
Mileant, A., Simon, M.
core +1 more source
Development of a TDC to equip a Liquid Xenon PET prototype
, 2005 A Time to Digital Converter was designed (CMOS 0.35 $\mum) in order to be used in Liquid Xenon PET prototype. The circuit proved to be able to work at -120 degrees C, while showing a resolution of 250 ps. The circuit enables a low readout dead time (
Bourrion, O., Gallin-Martel, L.
core +1 more source
Programmable rate modem utilizing digital signal processing techniques [PDF]
The engineering development study to follow was written to address the need for a Programmable Rate Digital Satellite Modem capable of supporting both burst and continuous transmission modes with either binary phase shift keying (BPSK) or quadrature ...
Bunya, George K., Wallace, Robert L.
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ALL Digital Phase-Locked Loop (ADPLL): A Survey
International Journal of Future Computer and Communication, 2013 Kusum Lata, Manoj Kumar
openaire +1 more source
A design study for an optimal non-linear receiver/demodulator Final report [PDF]
Design study for optimal nonlinear receiver ...
Bucy, R. S. +2 more
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A comparison of methods for DPLL loop filter design [PDF]
Four design methodologies for loop filters for a class of digital phase-locked loops (DPLLs) are presented. The first design maps an optimum analog filter into the digital domain; the second approach designs a filter that minimizes in discrete time ...
Aguirre, S. +3 more
core +1 more source
Application of multirate digital filter banks to wideband all-digital phase-locked loops design [PDF]
A new class of architecture for all-digital phase-locked loops (DPLL's) is presented in this article. These architectures, referred to as parallel DPLL (PDPLL), employ multirate digital filter banks (DFB's) to track signals with a lower processing rate ...
Hinedi, S., Sadr, R., Shah, B.
core +1 more source
An Overview of Phase-Locked Loop: From Fundamentals to the Frontier. [PDF]
Sensors (Basel)Nguyen TVH, Pham CK.
europepmc +1 more source
A State-Space Framework for Parallelizing Digital Signal Processing in Coherent Optical Receivers. [PDF]
Sensors (Basel)Wang J, Wang Z, Liu D.
europepmc +1 more source